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IB/mthca: Fix timeout for INIT_HCA and a few other commands 

Commands INIT_HCA, CLOSE_HCA, SYS_EN, SYS_DIS, and CLOSE_IB all have 1
second timeouts.  For INIT_HCA this causes problems when had more than
2^18 are QPs configured, since the command takes more than 1 second to
complete.

All other commands have 60-second timeouts.  This patch makes the
above commands consistent with the rest of the commands (and with the
chip documentation).

This patch is an expansion of a patch from Arthur Kepner
<akepner@sgi.com> fixing just the INIT_HCA timeout.

Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
hifive-unleashed-5.1
Jack Morgenstein 2009-04-20 21:12:25 -07:00 committed by Roland Dreier
parent a939b96ccc
commit 8531f1f14a
1 changed files with 9 additions and 7 deletions
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16
drivers/infiniband/hw/mthca/mthca_cmd.c
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@ -157,13 +157,15 @@ enum {
enum {
CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1
CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
CMD_TIME_CLASS_D = 60 * HZ
};
#else
enum {
CMD_TIME_CLASS_A = 60 * HZ,
CMD_TIME_CLASS_B = 60 * HZ,
CMD_TIME_CLASS_C = 60 * HZ
CMD_TIME_CLASS_C = 60 * HZ,
CMD_TIME_CLASS_D = 60 * HZ
};
#endif
@ -598,7 +600,7 @@ int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
u64 out;
int ret;
ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status);
if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
@ -611,7 +613,7 @@ int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
{
return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
}
static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
@ -1390,7 +1392,7 @@ int mthca_INIT_HCA(struct mthca_dev *dev,
MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
}
err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status);
mthca_free_mailbox(dev, mailbox);
return err;
@ -1450,12 +1452,12 @@ int mthca_INIT_IB(struct mthca_dev *dev,
int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
{
return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status);
}
int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
{
return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status);
}
int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,