ARM: devicetree updates for v5.7
Most of the commits are for additional hardware support and minor fixes
for existing machines for all the usual platforms: qcom, amlogic, at91,
gemini, mediatek, ti, socfpga, i.mx, layerscape, uniphier, rockchip,
exynos, ux500, mvebu, tegra, stm32, renesas, sunxi, broadcom, omap,
and versatile.
The conversion of binding files to machine-readable yaml format
continues, along with fixes found during the validation.
Andre Przywara takes over maintainership for the old Calxeda Highbank
platform and provides a number of updates.
The OMAP2+ platforms see a continued move from platform data into
dts files, for many devices that relied on a mix of auxiliary data
in addition to the DT description
A moderate number of new SoCs and machines are added, here is a full
list:
- Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865
(SM8250) is the current high-end phone chip, and IPQ6018 is a new
WiFi-6 router chip.
- Mediatek MT8516 application processor SoC for voice assistants, along
with the "pumpkin" development board
- NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an
evaluation board.
- Kontron "sl28" board family based on NXP LS1028A
- Eleven variations of the new i.MX6 TechNexion Pico board, combining
the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7
SoM carriers
- Three additional variants of the Toradex Colibri board family, all
based on versions of the NXP i.MX7.
- The Pinebook Pro laptop based on Rockchip RK3399
- Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based on
the ST-Ericsson u8500 platform
- DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on
STMicroelectronics stm32mp157
- Renesas M3ULCB starter kit for R-Car M3-W+
- Hoperun HiHope development board with Renesas RZ/G2M
- Pine64 PineTab tablet and PinePhone phone, both based on Allwinner A64
- Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner A20
- PocketBook Touch Lux 3 ebook reader, based on Allwinner A13
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"Most of the commits are for additional hardware support and minor
fixes for existing machines for all the usual platforms: qcom,
amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape,
uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas,
sunxi, broadcom, omap, and versatile.
The conversion of binding files to machine-readable yaml format
continues, along with fixes found during the validation. Andre
Przywara takes over maintainership for the old Calxeda Highbank
platform and provides a number of updates.
The OMAP2+ platforms see a continued move from platform data into dts
files, for many devices that relied on a mix of auxiliary data in
addition to the DT description
A moderate number of new SoCs and machines are added, here is a full
list:
- Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865
(SM8250) is the current high-end phone chip, and IPQ6018 is a new
WiFi-6 router chip.
- Mediatek MT8516 application processor SoC for voice assistants,
along with the "pumpkin" development board
- NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an
evaluation board.
- Kontron "sl28" board family based on NXP LS1028A
- Eleven variations of the new i.MX6 TechNexion Pico board, combining
the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7
SoM carriers
- Three additional variants of the Toradex Colibri board family, all
based on versions of the NXP i.MX7.
- The Pinebook Pro laptop based on Rockchip RK3399
- Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based
on the ST-Ericsson u8500 platform
- DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on
STMicroelectronics stm32mp157
- Renesas M3ULCB starter kit for R-Car M3-W+
- Hoperun HiHope development board with Renesas RZ/G2M
- Pine64 PineTab tablet and PinePhone phone, both based on Allwinner
A64
- Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner
A20
- PocketBook Touch Lux 3 ebook reader, based on Allwinner A13"
* tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits)
ARM: dts: ux500: Fix missing node renames
arm64: dts: Revert "specify console via command line"
MAINTAINERS: Update Calxeda Highbank maintainership
arm: dts: calxeda: Group port-phys and sgpio-gpio items
arm: dts: calxeda: Fix interrupt grouping
arm: dts: calxeda: Provide UART clock
arm: dts: calxeda: Basic DT file fixes
arm64: dts: specify console via command line
ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node
ARM: dts: gemini: Add thermal zone to DIR-685
ARM: dts: gemini: Rename IDE nodes
ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes
arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes
arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
arm64: dts: khadas-vim3: add SPIFC controller node
...
alistair/sensors
Linus Torvalds
commit
854e80bcfd
|
|
@ -0,0 +1,86 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Integrator Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
These were the first ARM platforms officially supported by ARM Ltd.
|
||||
They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
|
||||
so the system is modular and can host a variety of CPU tiles called
|
||||
"core tiles" and referred to in the device tree as "core modules".
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: ARM Integrator Application Platform, this board has a PCI
|
||||
host and several PCI slots, as well as a number of slots for logical
|
||||
expansion modules, it is referred to as an "ASIC Development
|
||||
Motherboard" and is extended with custom FPGA and is intended for
|
||||
rapid prototyping. See ARM DUI 0098B. This board can physically come
|
||||
pre-packaged in a PC Tower form factor called Integrator/PP1 or a
|
||||
special metal fixture called Integrator/PP2, see ARM DUI 0169A.
|
||||
items:
|
||||
- const: arm,integrator-ap
|
||||
- description: ARM Integrator Compact Platform (HBI-0086), this board has
|
||||
a compact form factor and mainly consists of the bare minimum
|
||||
peripherals to make use of the core module. See ARM DUI 0159B.
|
||||
items:
|
||||
- const: arm,integrator-cp
|
||||
- description: ARM Integrator Standard Development Board (SDB) Platform,
|
||||
this board is a PCI-based board conforming to the Microsoft SDB
|
||||
(HARP) specification. See ARM DUI 0099A.
|
||||
items:
|
||||
- const: arm,integrator-sp
|
||||
|
||||
core-module@10000000:
|
||||
type: object
|
||||
description: the root node in the Integrator platforms must contain
|
||||
a core module child node. They are always at physical address
|
||||
0x10000000 in all the Integrator variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,core-module-integrator
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^syscon@[0-9a-f]+$":
|
||||
description: All Integrator boards must provide a system controller as a
|
||||
node in the root of the device tree.
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,integrator-ap-syscon
|
||||
- arm,integrator-cp-syscon
|
||||
- arm,integrator-sp-syscon
|
||||
- const: syscon
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- core-module@10000000
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM RealView Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
The ARM RealView series of reference designs were built to explore the ARM
|
||||
11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
|
||||
the earlier CPUs such as TrustZone and multicore (MPCore).
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: ARM RealView Emulation Baseboard (HBI-0140) was created
|
||||
as a generic platform to test different FPGA designs, and has
|
||||
pluggable CPU modules, see ARM DUI 0303E.
|
||||
items:
|
||||
- const: arm,realview-eb
|
||||
- description: ARM RealView Platform Baseboard for ARM1176JZF-S
|
||||
(HBI-0147) was created as a development board to test ARM TrustZone,
|
||||
CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
|
||||
items:
|
||||
- const: arm,realview-pb1176
|
||||
- description: ARM RealView Platform Baseboard for ARM 11 MPCore
|
||||
(HBI-0159, HBI-0175 and HBI-0176) was created to showcase
|
||||
multiprocessing with ARM11 using MPCore using symmetric
|
||||
multiprocessing (SMP). See ARM DUI 0351E.
|
||||
items:
|
||||
- const: arm,realview-pb11mp
|
||||
- description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
|
||||
HBI-0176 and HBI-0175) was the first reference platform for the
|
||||
Cortex CPU family, including a Cortex-A8 test chip.
|
||||
items:
|
||||
- const: arm,realview-pba8
|
||||
- description: ARM RealView Platform Baseboard Explore for Cortex-A9
|
||||
(HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
|
||||
CPU.
|
||||
items:
|
||||
- const: arm,realview-pbx
|
||||
|
||||
soc:
|
||||
description: All RealView boards must provide a soc node in the root of the
|
||||
device tree, representing the System-on-Chip since these test chips are
|
||||
rather complex.
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,realview-eb-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pb1176-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pb11mp-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pba8-soc
|
||||
- const: simple-bus
|
||||
- items:
|
||||
- const: arm,realview-pbx-soc
|
||||
- const: simple-bus
|
||||
|
||||
patternProperties:
|
||||
"^.*syscon@[0-9a-f]+$":
|
||||
type: object
|
||||
description: All RealView boards must provide a syscon system controller
|
||||
node inside the soc node.
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,realview-eb11mp-revb-syscon
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-eb11mp-revc-syscon
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-eb-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pb1176-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pb11mp-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pba8-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: arm,realview-pbx-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- soc
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
|
||||
with various pluggable interface boards, in essence the Versatile PB version
|
||||
is a superset of the Versatile AB version.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The ARM Versatile Application Baseboard (HBI-0118) is an
|
||||
evaluation board specifically for the ARM926EJ-S. It can be connected
|
||||
to an IB1 interface board for a touchscreen-type use case or an IB2
|
||||
for a candybar phone-type use case. See ARM DUI 0225D.
|
||||
items:
|
||||
- const: arm,versatile-ab
|
||||
- description: The ARM Versatile Platform Baseboard (HBI-0117) is an
|
||||
extension of the Versatile Application Baseboard that includes a
|
||||
PCI host controller. Like the sibling board, it is done specifically
|
||||
for ARM926EJ-S. See ARM DUI 0224B.
|
||||
items:
|
||||
- const: arm,versatile-pb
|
||||
|
||||
core-module@10000000:
|
||||
type: object
|
||||
description: the root node in the Versatile platforms must contain
|
||||
a core module child node. They are always at physical address
|
||||
0x10000000 in all the Versatile variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,core-module-versatile
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^syscon@[0-9a-f]+$":
|
||||
type: object
|
||||
description: When fitted with the IB2 Interface Board, the Versatile
|
||||
AB will present an optional system controller node which controls the
|
||||
extra peripherals on the interface board.
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,versatile-ib2-syscon
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- core-module@10000000
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express and Juno Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Sudeep Holla <sudeep.holla@arm.com>
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |+
|
||||
ARM's Versatile Express platform were built as reference designs for exploring
|
||||
multicore Cortex-A class systems. The Versatile Express family contains both
|
||||
32 bit (Aarch32) and 64 bit (Aarch64) systems.
|
||||
|
||||
The board consist of a motherboard and one or more daughterboards (tiles). The
|
||||
motherboard provides a set of peripherals. Processor and RAM "live" on the
|
||||
tiles.
|
||||
|
||||
The motherboard and each core tile should be described by a separate Device
|
||||
Tree source file, with the tile's description including the motherboard file
|
||||
using an include directive. As the motherboard can be initialized in one of
|
||||
two different configurations ("memory maps"), care must be taken to include
|
||||
the correct one.
|
||||
|
||||
When a new generation of boards were introduced under the name "Juno", these
|
||||
shared to many common characteristics with the Versatile Express that the
|
||||
"arm,vexpress" compatible was retained in the root node, and these are
|
||||
included in this binding schema as well.
|
||||
|
||||
The root node indicates the CPU SoC on the core tile, and this
|
||||
is a daughterboard to the main motherboard. The name used in the compatible
|
||||
string shall match the name given in the core tile's technical reference
|
||||
manual, followed by "arm,vexpress" as an additional compatible value. If
|
||||
further subvariants are released of the core tile, even more fine-granular
|
||||
compatible strings with up to three compatible strings are used.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
|
||||
in MPCore configuration in a test chip on the core tile. See ARM
|
||||
DUI 0448I. This was the first Versatile Express platform.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca9
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
|
||||
in a test chip on the core tile. It is intended to evaluate NEON, FPU
|
||||
and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca5s
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
|
||||
cores in a MPCore configuration in a test chip on the core tile. See
|
||||
ARM DUI 0604F.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
|
||||
A15 CPU cores in a test chip on the core tile. This is the first test
|
||||
chip called "TC1".
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15,tc1
|
||||
- const: arm,vexpress,v2p-ca15
|
||||
- const: arm,vexpress
|
||||
- description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
|
||||
CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
|
||||
in a test chip on the core tile. See ARM DDI 0503I.
|
||||
items:
|
||||
- const: arm,vexpress,v2p-ca15_a7
|
||||
- const: arm,vexpress
|
||||
- description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
|
||||
cores in a test chip on the core tile. See ARM DDI 0498D.
|
||||
items:
|
||||
- const: arm,vexpress,v2f-1xv7,ca53x2
|
||||
- const: arm,vexpress,v2f-1xv7
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno "r0" (the first Juno board,
|
||||
V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
|
||||
AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
|
||||
cores in a big.LITTLE configuration. It also features the MALI T624
|
||||
GPU. See ARM document 100113_0000_07_en.
|
||||
items:
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r1 Development Platform
|
||||
(V2M-Juno r1) was introduced mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on
|
||||
the TLX connectors to join the coherency domain. Otherwise it is the
|
||||
same configuration as Juno r0. See ARM document 100122_0100_06_en.
|
||||
items:
|
||||
- const: arm,juno-r1
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm Versatile Express Juno r2 Development Platform
|
||||
(V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
|
||||
ARM document 100114_0200_04_en.
|
||||
items:
|
||||
- const: arm,juno-r2
|
||||
- const: arm,juno
|
||||
- const: arm,vexpress
|
||||
- description: Arm AEMv8a Versatile Express Real-Time System Model
|
||||
(VE RTSM) is a programmers view of the Versatile Express with Arm
|
||||
v8A hardware. See ARM DUI 0575D.
|
||||
items:
|
||||
- const: arm,rtsm_ve,aemv8a
|
||||
- const: arm,vexpress
|
||||
- description: Arm FVP (Fixed Virtual Platform) base model revision C
|
||||
See ARM Document 100964_1190_00_en.
|
||||
items:
|
||||
- const: arm,fvp-base-revc
|
||||
- const: arm,vexpress
|
||||
- description: Arm Foundation model for Aarch64
|
||||
items:
|
||||
- const: arm,foundation-aarch64
|
||||
- const: arm,vexpress
|
||||
|
||||
arm,hbi:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: This indicates the ARM HBI (Hardware Board ID), this is
|
||||
ARM's unique board model ID, visible on the PCB's silkscreen.
|
||||
|
||||
arm,vexpress,site:
|
||||
description: As Versatile Express can be configured in number of physically
|
||||
different setups, the device tree should describe platform topology.
|
||||
For this reason the root node and main motherboard node must define this
|
||||
property, describing the physical location of the children nodes.
|
||||
0 means motherboard site, while 1 and 2 are daughterboard sites, and
|
||||
0xf means "sisterboard" which is the site containing the main CPU tile.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 15
|
||||
|
||||
arm,vexpress,position:
|
||||
description: When daughterboards are stacked on one site, their position
|
||||
in the stack be be described this attribute.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 3
|
||||
|
||||
arm,vexpress,dcc:
|
||||
description: When describing tiles consisting of more than one DCC, its
|
||||
number can be specified with this attribute.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- minimum: 0
|
||||
maximum: 3
|
||||
|
||||
patternProperties:
|
||||
"^bus@[0-9a-f]+$":
|
||||
description: Static Memory Bus (SMB) node, if this exists it describes
|
||||
the connection between the motherboard and any tiles. Sometimes the
|
||||
compatible is placed directly under this node, sometimes it is placed
|
||||
in a subnode named "motherboard". Sometimes the compatible includes
|
||||
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
|
||||
"simple-bus". If the compatible is placed in the "motherboard" node,
|
||||
it is stricter and always has two compatibles.
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: '/schemas/simple-bus.yaml'
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
- const: simple-bus
|
||||
motherboard:
|
||||
type: object
|
||||
description: The motherboard description provides a single "motherboard"
|
||||
node using 2 address cells corresponding to the Static Memory Bus
|
||||
used between the motherboard and the tile. The first cell defines the
|
||||
Chip Select (CS) line number, the second cell address offset within
|
||||
the CS. All interrupt lines between the motherboard and the tile
|
||||
are active high and are described using single cell.
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 2
|
||||
"#size-cells":
|
||||
const: 1
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,vexpress,v2m-p1
|
||||
- arm,vexpress,v2p-p1
|
||||
- const: simple-bus
|
||||
arm,v2m-memory-map:
|
||||
description: This describes the memory map type.
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/string'
|
||||
- enum:
|
||||
- rs1
|
||||
- rs2
|
||||
required:
|
||||
- compatible
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,vexpress,v2p-ca9
|
||||
- arm,vexpress,v2p-ca5s
|
||||
- arm,vexpress,v2p-ca15
|
||||
- arm,vexpress,v2p-ca15_a7
|
||||
- arm,vexpress,v2f-1xv7,ca53x2
|
||||
then:
|
||||
required:
|
||||
- arm,hbi
|
||||
|
||||
...
|
||||
|
|
@ -1,237 +0,0 @@
|
|||
ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
|
||||
-----------------------------------------------------------------------------
|
||||
ARM's oldest Linux-supported platform with connectors for different core
|
||||
tiles of ARMv4, ARMv5 and ARMv6 type.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,integrator-ap"; /* Application Platform */
|
||||
compatible = "arm,integrator-cp"; /* Compact Platform */
|
||||
|
||||
FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
|
||||
|
||||
Required nodes:
|
||||
|
||||
- core-module: the root node to the Integrator platforms must have
|
||||
a core-module with regs and the compatible string
|
||||
"arm,core-module-integrator"
|
||||
- external-bus-interface: the root node to the Integrator platforms
|
||||
must have an external bus interface with regs and the
|
||||
compatible-string "arm,external-bus-interface"
|
||||
|
||||
Required properties for the core module:
|
||||
- regs: the location and size of the core module registers, one
|
||||
range of 0x200 bytes.
|
||||
|
||||
- syscon: the root node of the Integrator platforms must have a
|
||||
system controller node pointing to the control registers,
|
||||
with the compatible string
|
||||
"arm,integrator-ap-syscon"
|
||||
"arm,integrator-cp-syscon"
|
||||
respectively.
|
||||
|
||||
Required properties for the system controller:
|
||||
- regs: the location and size of the system controller registers,
|
||||
one range of 0x100 bytes.
|
||||
|
||||
Required properties for the AP system controller:
|
||||
- interrupts: the AP syscon node must include the logical module
|
||||
interrupts, stated in order of module instance <module 0>,
|
||||
<module 1>, <module 2> ... for the CP system controller this
|
||||
is not required not of any use.
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "integrator.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Integrator/AP";
|
||||
compatible = "arm,integrator-ap";
|
||||
|
||||
core-module@10000000 {
|
||||
compatible = "arm,core-module-integrator";
|
||||
reg = <0x10000000 0x200>;
|
||||
};
|
||||
|
||||
ebi@12000000 {
|
||||
compatible = "arm,external-bus-interface";
|
||||
reg = <0x12000000 0x100>;
|
||||
};
|
||||
|
||||
syscon {
|
||||
compatible = "arm,integrator-ap-syscon";
|
||||
reg = <0x11000000 0x100>;
|
||||
interrupt-parent = <&pic>;
|
||||
/* These are the logic module IRQs */
|
||||
interrupts = <9>, <10>, <11>, <12>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
ARM Versatile Application and Platform Baseboards
|
||||
-------------------------------------------------
|
||||
ARM's development hardware platform with connectors for customizable
|
||||
core tiles. The hardware configuration of the Versatile boards is
|
||||
highly customizable.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,versatile-ab"; /* Application baseboard */
|
||||
compatible = "arm,versatile-pb"; /* Platform baseboard */
|
||||
|
||||
Interrupt controllers:
|
||||
- VIC required properties:
|
||||
compatible = "arm,versatile-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
- SIC required properties:
|
||||
compatible = "arm,versatile-sic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
Required nodes:
|
||||
|
||||
- core-module: the root node to the Versatile platforms must have
|
||||
a core-module with regs and the compatible strings
|
||||
"arm,core-module-versatile", "syscon"
|
||||
|
||||
Optional nodes:
|
||||
|
||||
- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
|
||||
board mounted, this has a separate system controller that is
|
||||
defined in this node.
|
||||
Required properties:
|
||||
compatible = "arm,versatile-ib2-syscon", "syscon"
|
||||
|
||||
ARM RealView Boards
|
||||
-------------------
|
||||
The RealView boards cover tailored evaluation boards that are used to explore
|
||||
the ARM11 and Cortex A-8 and Cortex A-9 processors.
|
||||
|
||||
Required properties (in root node):
|
||||
/* RealView Emulation Baseboard */
|
||||
compatible = "arm,realview-eb";
|
||||
/* RealView Platform Baseboard for ARM1176JZF-S */
|
||||
compatible = "arm,realview-pb1176";
|
||||
/* RealView Platform Baseboard for ARM11 MPCore */
|
||||
compatible = "arm,realview-pb11mp";
|
||||
/* RealView Platform Baseboard for Cortex A-8 */
|
||||
compatible = "arm,realview-pba8";
|
||||
/* RealView Platform Baseboard Explore for Cortex A-9 */
|
||||
compatible = "arm,realview-pbx";
|
||||
|
||||
Required nodes:
|
||||
|
||||
- soc: some node of the RealView platforms must be the SoC
|
||||
node that contain the SoC-specific devices, with the compatible
|
||||
string set to one of these tuples:
|
||||
"arm,realview-eb-soc", "simple-bus"
|
||||
"arm,realview-pb1176-soc", "simple-bus"
|
||||
"arm,realview-pb11mp-soc", "simple-bus"
|
||||
"arm,realview-pba8-soc", "simple-bus"
|
||||
"arm,realview-pbx-soc", "simple-bus"
|
||||
|
||||
- syscon: some subnode of the RealView SoC node must be a
|
||||
system controller node pointing to the control registers,
|
||||
with the compatible string set to one of these:
|
||||
"arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-eb-syscon", "syscon"
|
||||
"arm,realview-pb1176-syscon", "syscon"
|
||||
"arm,realview-pb11mp-syscon", "syscon"
|
||||
"arm,realview-pba8-syscon", "syscon"
|
||||
"arm,realview-pbx-syscon", "syscon"
|
||||
|
||||
Required properties for the system controller:
|
||||
- regs: the location and size of the system controller registers,
|
||||
one range of 0x1000 bytes.
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "ARM RealView PB1176 with device tree";
|
||||
compatible = "arm,realview-pb1176";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,realview-pb1176-soc", "simple-bus";
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-syscon", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
ARM Versatile Express Boards
|
||||
-----------------------------
|
||||
For details on the device tree bindings for ARM Versatile Express boards
|
||||
please consult the vexpress.txt file in the same directory as this file.
|
||||
|
||||
ARM Juno Boards
|
||||
----------------
|
||||
The Juno boards are targeting development for AArch64 systems. The first
|
||||
iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
|
||||
with the second iteration, Juno r1, mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on the TLX
|
||||
connectors to join the coherency domain.
|
||||
|
||||
Juno boards are described in a similar way to ARM Versatile Express boards,
|
||||
with the motherboard part of the hardware being described in a separate file
|
||||
to highlight the fact that is part of the support infrastructure for the SoC.
|
||||
Juno device tree bindings also share the Versatile Express bindings as
|
||||
described under the RS1 memory mapping.
|
||||
|
||||
Required properties (in root node):
|
||||
compatible = "arm,juno"; /* For Juno r0 board */
|
||||
compatible = "arm,juno-r1"; /* For Juno r1 board */
|
||||
compatible = "arm,juno-r2"; /* For Juno r2 board */
|
||||
|
||||
Required nodes:
|
||||
The description for the board must include:
|
||||
- a "psci" node describing the boot method used for the secondary CPUs.
|
||||
A detailed description of the bindings used for "psci" nodes is present
|
||||
in the psci.yaml file.
|
||||
- a "cpus" node describing the available cores and their associated
|
||||
"enable-method"s. For more details see cpus.yaml file.
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "ARM Juno development board (r0)";
|
||||
compatible = "arm,juno", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
.....
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
.....
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm11351-cpu-method";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
Broadcom BCM11351 device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
|
||||
bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible = "brcm,bcm11351";
|
||||
DEPRECATED: compatible = "bcm,bcm11351";
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM11351 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm28155-ap
|
||||
- const: brcm,bcm11351
|
||||
|
||||
...
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
Broadcom BCM21664 device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
This document describes the device tree bindings for boards with the BCM21664
|
||||
SoC.
|
||||
|
||||
Required root node property:
|
||||
- compatible: brcm,bcm21664
|
||||
|
||||
Example:
|
||||
/ {
|
||||
model = "BCM21664 SoC";
|
||||
compatible = "brcm,bcm21664";
|
||||
[...]
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM21664 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm21664-garnet
|
||||
- const: brcm,bcm21664
|
||||
|
||||
...
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM23550
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm23550";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
enable-method = "brcm,bcm23550";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
Broadcom BCM23550 device tree bindings
|
||||
--------------------------------------
|
||||
|
||||
This document describes the device tree bindings for boards with the BCM23550
|
||||
SoC.
|
||||
|
||||
Required root node property:
|
||||
- compatible: brcm,bcm23550
|
||||
|
||||
Example:
|
||||
/ {
|
||||
model = "BCM23550 SoC";
|
||||
compatible = "brcm,bcm23550";
|
||||
[...]
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM23550 device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm23550-sparrow
|
||||
- const: brcm,bcm23550
|
||||
|
||||
...
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
Broadcom BCM4708 device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the BCM4708 SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
bcm4708
|
||||
compatible = "brcm,bcm4708";
|
||||
|
||||
bcm4709
|
||||
compatible = "brcm,bcm4709";
|
||||
|
||||
bcm53012
|
||||
compatible = "brcm,bcm53012";
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM4708 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
|
||||
on the iProc architecture (Northstar).
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
- Rafal Milecki <zajec5@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM4708 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac56u
|
||||
- asus,rt-ac68u
|
||||
- buffalo,wzr-1750dhp
|
||||
- linksys,ea6300-v1
|
||||
- linksys,ea6500-v2
|
||||
- luxul,xap-1510v1
|
||||
- luxul,xwc-1000
|
||||
- netgear,r6250v1
|
||||
- netgear,r6300v2
|
||||
- smartrg,sr400ac
|
||||
- brcm,bcm94708
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47081 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-n18u
|
||||
- buffalo,wzr-600dhp2
|
||||
- buffalo,wzr-900dhp
|
||||
- luxul,xap-1410v1
|
||||
- luxul,xwr-1200v1
|
||||
- tplink,archer-c5-v2
|
||||
- const: brcm,bcm47081
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM4709 based boards
|
||||
items:
|
||||
- enum:
|
||||
- asus,rt-ac87u
|
||||
- buffalo,wxr-1900dhp
|
||||
- linksys,ea9200
|
||||
- netgear,r7000
|
||||
- netgear,r8000
|
||||
- tplink,archer-c9-v1
|
||||
- brcm,bcm94709
|
||||
- const: brcm,bcm4709
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM47094 based boards
|
||||
items:
|
||||
- enum:
|
||||
- dlink,dir-885l
|
||||
- linksys,panamera
|
||||
- luxul,abr-4500-v1
|
||||
- luxul,xap-1610-v1
|
||||
- luxul,xbr-4500-v1
|
||||
- luxul,xwc-2000-v1
|
||||
- luxul,xwr-3100v1
|
||||
- luxul,xwr-3150-v1
|
||||
- netgear,r8500
|
||||
- phicomm,k3
|
||||
- const: brcm,bcm47094
|
||||
- const: brcm,bcm4708
|
||||
|
||||
- description: BCM53012 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm953012er
|
||||
- brcm,bcm953012hr
|
||||
- brcm,bcm953012k
|
||||
- const: brcm,brcm53012
|
||||
- const: brcm,bcm4708
|
||||
...
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
Broadcom Cygnus device tree bindings
|
||||
------------------------------------
|
||||
|
||||
|
||||
Boards with Cygnus SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM11300
|
||||
compatible = "brcm,bcm11300", "brcm,cygnus";
|
||||
|
||||
BCM11320
|
||||
compatible = "brcm,bcm11320", "brcm,cygnus";
|
||||
|
||||
BCM11350
|
||||
compatible = "brcm,bcm11350", "brcm,cygnus";
|
||||
|
||||
BCM11360
|
||||
compatible = "brcm,bcm11360", "brcm,cygnus";
|
||||
|
||||
BCM58300
|
||||
compatible = "brcm,bcm58300", "brcm,cygnus";
|
||||
|
||||
BCM58302
|
||||
compatible = "brcm,bcm58302", "brcm,cygnus";
|
||||
|
||||
BCM58303
|
||||
compatible = "brcm,bcm58303", "brcm,cygnus";
|
||||
|
||||
BCM58305
|
||||
compatible = "brcm,bcm58305", "brcm,cygnus";
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Cygnus device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm11300
|
||||
- brcm,bcm11320
|
||||
- brcm,bcm11350
|
||||
- brcm,bcm11360
|
||||
- brcm,bcm58300
|
||||
- brcm,bcm58302
|
||||
- brcm,bcm58303
|
||||
- brcm,bcm58305
|
||||
- const: brcm,cygnus
|
||||
|
||||
...
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
Broadcom Hurricane 2 device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
|
||||
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
|
||||
flash and a PCIe attached integrated switching engine.
|
||||
|
||||
Boards with Hurricane SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM53342
|
||||
compatible = "brcm,bcm53342", "brcm,hr2";
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Hurricane 2 device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
are based on Broadcom's iProc SoC architecture and feature a single core Cortex
|
||||
A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
|
||||
flash and a PCIe attached integrated switching engine.
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ubnt,unifi-switch8
|
||||
- const: brcm,bcm53342
|
||||
- const: brcm,hr2
|
||||
|
||||
...
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
Broadcom North Star 2 (NS2) device tree bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with NS2 shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
NS2 SVK board
|
||||
compatible = "brcm,ns2-svk", "brcm,ns2";
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom North Star 2 (NS2) device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,ns2-svk
|
||||
- brcm,ns2-xmc
|
||||
- const: brcm,ns2
|
||||
|
||||
...
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
Broadcom Northstar Plus SoC CPU Enable Method
|
||||
---------------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPU in the following Broadcom SoCs:
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the corresponding secondary "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm-nsp-smp";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register which should hold the common
|
||||
entry point for a secondary CPU. This entry is cpu node specific
|
||||
and should be added per cpu. E.g., in case of NSP (BCM58625) which
|
||||
is a dual core CPU SoC, this entry should be added to cpu1 node.
|
||||
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
enable-method = "brcm,bcm-nsp-smp";
|
||||
secondary-boot-reg = <0xffff042c>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
Broadcom Northstar Plus device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
Boards with Northstar Plus SoCs shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
BCM58522
|
||||
compatible = "brcm,bcm58522", "brcm,nsp";
|
||||
|
||||
BCM58525
|
||||
compatible = "brcm,bcm58525", "brcm,nsp";
|
||||
|
||||
BCM58535
|
||||
compatible = "brcm,bcm58535", "brcm,nsp";
|
||||
|
||||
BCM58622
|
||||
compatible = "brcm,bcm58622", "brcm,nsp";
|
||||
|
||||
BCM58623
|
||||
compatible = "brcm,bcm58623", "brcm,nsp";
|
||||
|
||||
BCM58625
|
||||
compatible = "brcm,bcm58625", "brcm,nsp";
|
||||
|
||||
BCM88312
|
||||
compatible = "brcm,bcm88312", "brcm,nsp";
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Northstar Plus device tree bindings
|
||||
|
||||
description:
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm58522
|
||||
- brcm,bcm58525
|
||||
- brcm,bcm58535
|
||||
- brcm,bcm58622
|
||||
- brcm,bcm58623
|
||||
- brcm,bcm58625
|
||||
- brcm,bcm88312
|
||||
- const: brcm,nsp
|
||||
|
||||
...
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
Broadcom Stingray device tree bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with Stingray shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
Stingray Combo SVK board
|
||||
compatible = "brcm,bcm958742k", "brcm,stingray";
|
||||
|
||||
Stingray SST100 board
|
||||
compatible = "brcm,bcm958742t", "brcm,stingray";
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm958742k
|
||||
- brcm,bcm958742t
|
||||
- brcm,bcm958802a802x
|
||||
- const: brcm,stingray
|
||||
|
||||
...
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
Broadcom Vulcan device tree bindings
|
||||
------------------------------------
|
||||
|
||||
Boards with Broadcom Vulcan shall have the following root property:
|
||||
|
||||
Broadcom Vulcan Evaluation Board:
|
||||
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
|
||||
|
||||
Generic Vulcan board:
|
||||
compatible = "brcm,vulcan-soc";
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Vulcan device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rrichter@marvell.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,vulcan-eval
|
||||
- cavium,thunderx2-cn9900
|
||||
- const: brcm,vulcan-soc
|
||||
|
||||
...
|
||||
|
|
@ -300,6 +300,39 @@ properties:
|
|||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
|
||||
secondary-boot-reg:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: |
|
||||
Required for systems that have an "enable-method" property value of
|
||||
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
|
||||
|
||||
This includes the following SoCs: |
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
if:
|
||||
# If the enable-method property contains one of those values
|
||||
properties:
|
||||
enable-method:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm-nsp-smp
|
||||
# and if enable-method is present
|
||||
required:
|
||||
- enable-method
|
||||
|
||||
then:
|
||||
required:
|
||||
- secondary-boot-reg
|
||||
|
||||
required:
|
||||
- device_type
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -119,6 +119,10 @@ properties:
|
|||
- fsl,imx6q-sabreauto
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
|
||||
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
|
||||
- technologic,imx6q-ts4900
|
||||
- technologic,imx6q-ts7970
|
||||
- toradex,apalis_imx6q # Apalis iMX6 Module
|
||||
|
|
@ -166,6 +170,10 @@ properties:
|
|||
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
|
||||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- toradex,colibri_imx6dl # Colibri iMX6 Module
|
||||
|
|
@ -225,6 +233,9 @@ properties:
|
|||
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
|
||||
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
|
||||
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
|
||||
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
|
||||
- technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
|
||||
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S Board
|
||||
|
|
@ -274,6 +285,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
|
||||
- toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
|
||||
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
|
||||
- const: fsl,imx7s
|
||||
|
|
@ -284,8 +296,14 @@ properties:
|
|||
- fsl,imx7d-sdb # i.MX7 SabreSD Board
|
||||
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
|
||||
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
|
||||
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
|
||||
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
|
||||
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
|
||||
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
|
||||
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
|
||||
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
|
||||
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
|
||||
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
||||
|
|
@ -324,6 +342,12 @@ properties:
|
|||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -395,6 +419,51 @@ properties:
|
|||
- fsl,ls1021a-twr
|
||||
- const: fsl,ls1021a
|
||||
|
||||
- description: LS1028A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1028a-qds
|
||||
- fsl,ls1028a-rdb
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: Kontron KBox A-230-LS
|
||||
items:
|
||||
- const: kontron,kbox-a-230-ls
|
||||
- const: kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2-ads2
|
||||
- kontron,sl28-var3-ads2
|
||||
- kontron,sl28-var4-ads2
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (on a generic/undefined carrier)
|
||||
items:
|
||||
- enum:
|
||||
- kontron,sl28-var2
|
||||
- kontron,sl28-var3
|
||||
- kontron,sl28-var4
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description:
|
||||
Kontron SMARC-sAL28 board (base). This is used in the base device
|
||||
tree which is compatible with the overlays provided by the
|
||||
vendor.
|
||||
items:
|
||||
- const: kontron,sl28
|
||||
- const: fsl,ls1028a
|
||||
|
||||
- description: LS1043A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ description: |
|
|||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8916
|
||||
|
|
@ -41,6 +42,7 @@ description: |
|
|||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
cp01-c1
|
||||
dragonboard
|
||||
hk01
|
||||
idp
|
||||
|
|
@ -150,4 +152,10 @@ properties:
|
|||
- enum:
|
||||
- qcom,sc7180-idp
|
||||
- const: qcom,sc7180
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq6018-cp01-c1
|
||||
- const: qcom,ipq6018
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -208,6 +208,7 @@ properties:
|
|||
- description: R-Car M3-W+ (R8A77961)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP8J77961ASKB0SK0SA05A (M3 ES3.0))
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A)
|
||||
- const: renesas,r8a77961
|
||||
|
||||
|
|
|
|||
|
|
@ -402,6 +402,11 @@ properties:
|
|||
- const: phytec,rk3288-phycore-som
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Pine64 PinebookPro
|
||||
items:
|
||||
- const: pine64,pinebook-pro
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 Rock64
|
||||
items:
|
||||
- const: pine64,rock64
|
||||
|
|
@ -443,7 +448,7 @@ properties:
|
|||
|
||||
- description: Rockchip Kylin
|
||||
items:
|
||||
- const: rockchip,kylin-rk3036
|
||||
- const: rockchip,rk3036-kylin
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip PX3 Evaluation board
|
||||
|
|
@ -468,6 +473,11 @@ properties:
|
|||
- const: rockchip,r88
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Rockchip RK3036 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3036-evb
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip RK3228 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3228-evb
|
||||
|
|
|
|||
|
|
@ -394,6 +394,12 @@ properties:
|
|||
- const: linksprite,pcduino3-nano
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Linutronix Testbox v2
|
||||
items:
|
||||
- const: linutronix,testbox-v2
|
||||
- const: lamobo,lamobo-r1
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: HAOYU Electronics Marsboard A10
|
||||
items:
|
||||
- const: haoyu,a10-marsboard
|
||||
|
|
@ -636,6 +642,21 @@ properties:
|
|||
- const: pine64,pinebook
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone Developer Batch (1.0)
|
||||
items:
|
||||
- const: pine64,pinephone-1.0
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone Braveheart (1.1)
|
||||
items:
|
||||
- const: pine64,pinephone-1.1
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab
|
||||
items:
|
||||
- const: pine64,pinetab
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 SoPine Baseboard
|
||||
items:
|
||||
- const: pine64,sopine-baseboard
|
||||
|
|
@ -647,6 +668,11 @@ properties:
|
|||
- const: pineriver,mini-xplus
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: PocketBook Touch Lux 3
|
||||
items:
|
||||
- const: pocketbook,touch-lux-3
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Point of View Protab2-IPS9
|
||||
items:
|
||||
- const: pov,protab2-ips9
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
enum:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -1,229 +0,0 @@
|
|||
ARM Versatile Express boards family
|
||||
-----------------------------------
|
||||
|
||||
ARM's Versatile Express platform consists of a motherboard and one
|
||||
or more daughterboards (tiles). The motherboard provides a set of
|
||||
peripherals. Processor and RAM "live" on the tiles.
|
||||
|
||||
The motherboard and each core tile should be described by a separate
|
||||
Device Tree source file, with the tile's description including
|
||||
the motherboard file using a /include/ directive. As the motherboard
|
||||
can be initialized in one of two different configurations ("memory
|
||||
maps"), care must be taken to include the correct one.
|
||||
|
||||
|
||||
Root node
|
||||
---------
|
||||
|
||||
Required properties in the root node:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,<model>", "arm,vexpress";
|
||||
where <model> is the full tile model name (as used in the tile's
|
||||
Technical Reference Manual), eg.:
|
||||
- for Coretile Express A5x2 (V2P-CA5s):
|
||||
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
|
||||
- for Coretile Express A9x4 (V2P-CA9):
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
If a tile comes in several variants or can be used in more then one
|
||||
configuration, the compatible value should be:
|
||||
compatible = "arm,vexpress,<model>,<variant>", \
|
||||
"arm,vexpress,<model>", "arm,vexpress";
|
||||
eg:
|
||||
- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
|
||||
compatible = "arm,vexpress,v2p-ca15,tc1", \
|
||||
"arm,vexpress,v2p-ca15", "arm,vexpress";
|
||||
- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
|
||||
compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
|
||||
"arm,vexpress,v2f-2xv6", "arm,vexpress";
|
||||
|
||||
Optional properties in the root node:
|
||||
- tile model name (use name from the tile's Technical Reference
|
||||
Manual, eg. "V2P-CA5s")
|
||||
model = "<model>";
|
||||
- tile's HBI number (unique ARM's board model ID, visible on the
|
||||
PCB's silkscreen) in hexadecimal transcription:
|
||||
arm,hbi = <0xhbi>
|
||||
eg:
|
||||
- for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
|
||||
arm,hbi = <0x191>;
|
||||
- Coretile Express A9x4 (V2P-CA9) HBI-0225:
|
||||
arm,hbi = <0x225>;
|
||||
|
||||
|
||||
CPU nodes
|
||||
---------
|
||||
|
||||
Top-level standard "cpus" node is required. It must contain a node
|
||||
with device_type = "cpu" property for every available core, eg.:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Configuration infrastructure
|
||||
----------------------------
|
||||
|
||||
The platform has an elaborated configuration system, consisting of
|
||||
microcontrollers residing on the mother- and daughterboards known
|
||||
as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
|
||||
The controllers are responsible for the platform initialization
|
||||
(reset generation, flash programming, FPGA bitfiles loading etc.)
|
||||
but also control clock generators, voltage regulators, gather
|
||||
environmental data like temperature, power consumption etc. Even
|
||||
the video output switch (FPGA) is controlled that way.
|
||||
|
||||
The controllers are not mapped into normal memory address space
|
||||
and must be accessed through bridges - other devices capable
|
||||
of generating transactions on the configuration bus.
|
||||
|
||||
The nodes describing configuration controllers must define
|
||||
the following properties:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
- bridge phandle:
|
||||
arm,vexpress,config-bridge = <phandle>;
|
||||
and children describing available functions.
|
||||
|
||||
|
||||
Platform topology
|
||||
-----------------
|
||||
|
||||
As Versatile Express can be configured in number of physically
|
||||
different setups, the device tree should describe platform topology.
|
||||
Root node and main motherboard node must define the following
|
||||
property, describing physical location of the children nodes:
|
||||
- site number:
|
||||
arm,vexpress,site = <number>;
|
||||
where 0 means motherboard, 1 or 2 are daugtherboard sites,
|
||||
0xf means "master" site (site containing main CPU tile)
|
||||
- when daughterboards are stacked on one site, their position
|
||||
in the stack be be described with:
|
||||
arm,vexpress,position = <number>;
|
||||
- when describing tiles consisting more than one DCC, its number
|
||||
can be described with:
|
||||
arm,vexpress,dcc = <number>;
|
||||
|
||||
Any of the numbers above defaults to zero if not defined in
|
||||
the node or any of its parent.
|
||||
|
||||
|
||||
Motherboard
|
||||
-----------
|
||||
|
||||
The motherboard description file provides a single "motherboard" node
|
||||
using 2 address cells corresponding to the Static Memory Bus used
|
||||
between the motherboard and the tile. The first cell defines the Chip
|
||||
Select (CS) line number, the second cell address offset within the CS.
|
||||
All interrupt lines between the motherboard and the tile are active
|
||||
high and are described using single cell.
|
||||
|
||||
Optional properties of the "motherboard" node:
|
||||
- motherboard's memory map variant:
|
||||
arm,v2m-memory-map = "<name>";
|
||||
where name is one of:
|
||||
- "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
|
||||
referred to as "ARM Cortex-A Series memory map":
|
||||
arm,v2m-memory-map = "rs1";
|
||||
When this property is missing, the motherboard is using the original
|
||||
memory map (also known as the "Legacy memory map", primarily used
|
||||
with the original CoreTile Express A9x4) with peripherals on CS7.
|
||||
|
||||
Motherboard .dtsi files provide a set of labelled peripherals that
|
||||
can be used to obtain required phandle in the tile's "aliases" node:
|
||||
- UARTs, note that the numbers correspond to the physical connectors
|
||||
on the motherboard's back panel:
|
||||
v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
|
||||
- I2C controllers:
|
||||
v2m_i2c_dvi and v2m_i2c_pcie
|
||||
- SP804 timers:
|
||||
v2m_timer01 and v2m_timer23
|
||||
|
||||
The tile description should define a "smb" node, describing the
|
||||
Static Memory Bus between the tile and motherboard. It must define
|
||||
the following properties:
|
||||
- "simple-bus" compatible value (to ensure creation of the children)
|
||||
compatible = "simple-bus";
|
||||
- mapping of the SMB CS/offset addresses into main address space:
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <...>;
|
||||
- interrupts mapping:
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <...>;
|
||||
|
||||
|
||||
Example of a VE tile description (simplified)
|
||||
---------------------------------------------
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c000100 0x100>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* CS0 is visible at 0x08000000 */
|
||||
ranges = <0 0 0x08000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
/* Active high IRQ 0 is connected to GIC's SPI0 */
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -11,7 +11,7 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
dcp@80028000 {
|
||||
dcp: crypto@80028000 {
|
||||
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
|
||||
reg = <0x80028000 0x2000>;
|
||||
interrupts = <52 53>;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
sah@10025000 {
|
||||
sah: crypto@10025000 {
|
||||
compatible = "fsl,imx27-sahara";
|
||||
reg = < 0x10025000 0x800>;
|
||||
interrupts = <75>;
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@ iMX6QDL/SX requires four clocks
|
|||
|
||||
iMX6UL does only require three clocks
|
||||
|
||||
crypto: caam@2140000 {
|
||||
crypto: crypto@2140000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ Tegra194 RC mode:
|
|||
-----------------
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
|
|
|||
|
|
@ -18,9 +18,14 @@ properties:
|
|||
"#size-cells": true
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun6i-a31-spi
|
||||
- allwinner,sun8i-h3-spi
|
||||
oneOf:
|
||||
- const: allwinner,sun6i-a31-spi
|
||||
- const: allwinner,sun8i-h3-spi
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,sun8i-r40-spi
|
||||
- allwinner,sun50i-h6-spi
|
||||
- const: allwinner,sun8i-h3-spi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -1622,7 +1622,7 @@ F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
|
|||
F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
M: Andre Przywara <andre.przywara@arm.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-highbank/
|
||||
|
|
|
|||
|
|
@ -446,6 +446,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6dl-nitrogen6x.dtb \
|
||||
imx6dl-phytec-mira-rdk-nand.dtb \
|
||||
imx6dl-phytec-pbab01.dtb \
|
||||
imx6dl-pico-dwarf.dtb \
|
||||
imx6dl-pico-hobbit.dtb \
|
||||
imx6dl-pico-nymph.dtb \
|
||||
imx6dl-pico-pi.dtb \
|
||||
imx6dl-rex-basic.dtb \
|
||||
imx6dl-riotboard.dtb \
|
||||
imx6dl-sabreauto.dtb \
|
||||
|
|
@ -529,6 +533,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6q-phytec-mira-rdk-emmc.dtb \
|
||||
imx6q-phytec-mira-rdk-nand.dtb \
|
||||
imx6q-phytec-pbab01.dtb \
|
||||
imx6q-pico-dwarf.dtb \
|
||||
imx6q-pico-hobbit.dtb \
|
||||
imx6q-pico-nymph.dtb \
|
||||
imx6q-pico-pi.dtb \
|
||||
imx6q-pistachio.dtb \
|
||||
imx6q-rex-pro.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
|
|
@ -594,6 +602,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
|
|||
imx6ul-kontron-n6310-s-43.dtb \
|
||||
imx6ul-liteboard.dtb \
|
||||
imx6ul-opos6uldev.dtb \
|
||||
imx6ul-pico-dwarf.dtb \
|
||||
imx6ul-pico-hobbit.dtb \
|
||||
imx6ul-pico-pi.dtb \
|
||||
imx6ul-phytec-segin-ff-rdk-nand.dtb \
|
||||
|
|
@ -610,12 +619,16 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
|
|||
imx6ulz-14x14-evk.dtb
|
||||
dtb-$(CONFIG_SOC_IMX7D) += \
|
||||
imx7d-cl-som-imx7.dtb \
|
||||
imx7d-colibri-aster.dtb \
|
||||
imx7d-colibri-emmc-aster.dtb \
|
||||
imx7d-colibri-emmc-eval-v3.dtb \
|
||||
imx7d-colibri-eval-v3.dtb \
|
||||
imx7d-mba7.dtb \
|
||||
imx7d-meerkat96.dtb \
|
||||
imx7d-nitrogen7.dtb \
|
||||
imx7d-pico-dwarf.dtb \
|
||||
imx7d-pico-hobbit.dtb \
|
||||
imx7d-pico-nymph.dtb \
|
||||
imx7d-pico-pi.dtb \
|
||||
imx7d-sbc-imx7.dtb \
|
||||
imx7d-sdb.dtb \
|
||||
|
|
@ -623,6 +636,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
|
|||
imx7d-sdb-sht11.dtb \
|
||||
imx7d-zii-rmu2.dtb \
|
||||
imx7d-zii-rpu2.dtb \
|
||||
imx7s-colibri-aster.dtb \
|
||||
imx7s-colibri-eval-v3.dtb \
|
||||
imx7s-mba7.dtb \
|
||||
imx7s-warp.dtb
|
||||
|
|
@ -1016,6 +1030,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
|
|||
stm32h743i-disco.dtb \
|
||||
stm32mp157a-avenger96.dtb \
|
||||
stm32mp157a-dk1.dtb \
|
||||
stm32mp157c-dhcom-pdk2.dtb \
|
||||
stm32mp157c-dk2.dtb \
|
||||
stm32mp157c-ed1.dtb \
|
||||
stm32mp157c-ev1.dtb
|
||||
|
|
@ -1056,6 +1071,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
|
|||
sun5i-a13-licheepi-one.dtb \
|
||||
sun5i-a13-olinuxino.dtb \
|
||||
sun5i-a13-olinuxino-micro.dtb \
|
||||
sun5i-a13-pocketbook-touch-lux-3.dtb \
|
||||
sun5i-a13-q8-tablet.dtb \
|
||||
sun5i-a13-utoo-p66.dtb \
|
||||
sun5i-gr8-chip-pro.dtb \
|
||||
|
|
@ -1086,6 +1102,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
sun7i-a20-i12-tvbox.dtb \
|
||||
sun7i-a20-icnova-swac.dtb \
|
||||
sun7i-a20-lamobo-r1.dtb \
|
||||
sun7i-a20-linutronix-testbox-v2.dtb \
|
||||
sun7i-a20-m3.dtb \
|
||||
sun7i-a20-mk808c.dtb \
|
||||
sun7i-a20-olimex-som-evb.dtb \
|
||||
|
|
@ -1202,7 +1219,8 @@ dtb-$(CONFIG_ARCH_U8500) += \
|
|||
ste-hrefv60plus-stuib.dtb \
|
||||
ste-hrefv60plus-tvk.dtb \
|
||||
ste-href520-tvk.dtb \
|
||||
ste-ux500-samsung-golden.dtb
|
||||
ste-ux500-samsung-golden.dtb \
|
||||
ste-ux500-samsung-skomer.dtb
|
||||
dtb-$(CONFIG_ARCH_UNIPHIER) += \
|
||||
uniphier-ld4-ref.dtb \
|
||||
uniphier-ld6b-ref.dtb \
|
||||
|
|
|
|||
|
|
@ -759,12 +759,27 @@
|
|||
ranges = <0x0 0x200000 0x80000>;
|
||||
};
|
||||
|
||||
target-module@300000 { /* 0x4a300000, ap 9 04.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
|
||||
compatible = "ti,sysc-pruss", "ti,sysc";
|
||||
reg = <0x326000 0x4>,
|
||||
<0x326004 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
|
||||
SYSC_PRUSS_SUB_MWAIT)>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
resets = <&prm_per 1>;
|
||||
reset-names = "rstctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x300000 0x80000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
enable-method = "ti,am3352";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
|
|
@ -56,6 +57,17 @@
|
|||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
cpu-idle-states = <&mpu_gate>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
mpu_gate: mpu_gate {
|
||||
compatible = "arm,idle-state";
|
||||
entry-latency-us = <40>;
|
||||
exit-latency-us = <90>;
|
||||
min-residency-us = <300>;
|
||||
ti,idle-wkup-m3;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -193,45 +205,100 @@
|
|||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
ti,hwmods = "tpcc";
|
||||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
target-module@49000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49000000 0x10000>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@49800000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc0";
|
||||
reg = <0x49800000 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49800000 0x4>,
|
||||
<0x49800010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49800000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc1: tptc@49900000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc1";
|
||||
reg = <0x49900000 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc2: tptc@49a00000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc2";
|
||||
reg = <0x49a00000 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@47810000 {
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@
|
|||
#size-cells = <0>;
|
||||
cpu: cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
enable-method = "ti,am4372";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
|
|
@ -54,6 +55,17 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
cpu-idle-states = <&mpu_gate>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
mpu_gate: mpu_gate {
|
||||
compatible = "arm,idle-state";
|
||||
entry-latency-us = <40>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <300>;
|
||||
local-timer-stop;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -185,47 +197,102 @@
|
|||
&pm_sram_data>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
ti,hwmods = "tpcc";
|
||||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
target-module@49000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49000000 0x10000>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,edma-memcpy-channels = <58 59>;
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <58 59>;
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@49800000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc0";
|
||||
reg = <0x49800000 0x100000>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49800000 0x4>,
|
||||
<0x49800010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49800000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc1: tptc@49900000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc1";
|
||||
reg = <0x49900000 0x100000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc2: tptc@49a00000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc2";
|
||||
reg = <0x49a00000 0x100000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@47810000 {
|
||||
|
|
@ -344,6 +411,28 @@
|
|||
};
|
||||
};
|
||||
|
||||
pruss_tm: target-module@54400000 {
|
||||
compatible = "ti,sysc-pruss", "ti,sysc";
|
||||
reg = <0x54426000 0x4>,
|
||||
<0x54426004 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
|
||||
SYSC_PRUSS_SUB_MWAIT)>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
resets = <&prm_per 1>;
|
||||
reset-names = "rstctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x54400000 0x80000>;
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
|
|
@ -394,38 +483,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
dss: dss@4832a000 {
|
||||
compatible = "ti,omap3-dss";
|
||||
reg = <0x4832a000 0x200>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_core";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dispc: dispc@4832a400 {
|
||||
compatible = "ti,omap3-dispc";
|
||||
reg = <0x4832a400 0x400>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
|
||||
max-memory-bandwidth = <230000000>;
|
||||
};
|
||||
|
||||
rfbi: rfbi@4832a800 {
|
||||
compatible = "ti,omap3-rfbi";
|
||||
reg = <0x4832a800 0x100>;
|
||||
ti,hwmods = "dss_rfbi";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: sram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x40000>; /* 256k */
|
||||
|
|
|
|||
|
|
@ -2117,7 +2117,6 @@
|
|||
|
||||
target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
ti,hwmods = "dss_core";
|
||||
reg = <0x2a000 0x4>,
|
||||
<0x2a010 0x4>,
|
||||
<0x2a014 0x4>;
|
||||
|
|
@ -2135,6 +2134,82 @@
|
|||
<0x00000800 0x0002a800 0x00000400>,
|
||||
<0x00000c00 0x0002ac00 0x00000400>,
|
||||
<0x00001000 0x0002b000 0x00001000>;
|
||||
|
||||
dss: dss@0 {
|
||||
compatible = "ti,omap3-dss";
|
||||
reg = <0 0x200>;
|
||||
status = "disabled";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x00000400>,
|
||||
<0x00000400 0x00000400 0x00000400>,
|
||||
<0x00000800 0x00000800 0x00000400>,
|
||||
<0x00000c00 0x00000c00 0x00000400>,
|
||||
<0x00001000 0x00001000 0x00001000>;
|
||||
|
||||
target-module@400 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x400 0x4>,
|
||||
<0x410 0x4>,
|
||||
<0x414 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x400 0x400>;
|
||||
|
||||
dispc: dispc@0 {
|
||||
compatible = "ti,omap3-dispc";
|
||||
reg = <0 0x400>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
|
||||
max-memory-bandwidth = <230000000>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@800 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x800 0x4>,
|
||||
<0x810 0x4>,
|
||||
<0x814 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x800 0x400>;
|
||||
|
||||
rfbi: rfbi@0 {
|
||||
compatible = "ti,omap3-rfbi";
|
||||
reg = <0 0x100>;
|
||||
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Common PRUSS data for TI AM57xx platforms
|
||||
*/
|
||||
|
||||
&ocp {
|
||||
pruss1_tm: target-module@4b226000 {
|
||||
compatible = "ti,sysc-pruss", "ti,sysc";
|
||||
reg = <0x4b226000 0x4>,
|
||||
<0x4b226004 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
|
||||
SYSC_PRUSS_SUB_MWAIT)>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x4b200000 0x80000>;
|
||||
};
|
||||
|
||||
pruss2_tm: target-module@4b2a6000 {
|
||||
compatible = "ti,sysc-pruss", "ti,sysc";
|
||||
reg = <0x4b2a6000 0x4>,
|
||||
<0x4b2a6004 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
|
||||
SYSC_PRUSS_SUB_MWAIT)>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x4b280000 0x80000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "dra72x.dtsi"
|
||||
#include "am57-pruss.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am5718", "ti,dra7";
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "dra74x.dtsi"
|
||||
#include "am57-pruss.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am5728", "ti,dra7";
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "dra76x.dtsi"
|
||||
#include "am57-pruss.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am5748", "ti,dra762", "ti,dra7";
|
||||
|
|
|
|||
|
|
@ -210,7 +210,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
soc: soc {
|
||||
compatible = "arm,realview-pbx-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel";
|
||||
compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vcc_lcd_reg>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -645,3 +645,8 @@
|
|||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -186,6 +186,11 @@
|
|||
pinmux = <PIN_PA10__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
pinmux = <PIN_PA16__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
|
|
@ -248,6 +253,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0
|
||||
|
|
|
|||
|
|
@ -180,8 +180,11 @@
|
|||
|
||||
i2c0: i2c@f8028000 {
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -198,8 +201,11 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_flx0_default>;
|
||||
pinctrl-1 = <&pinctrl_flx0_gpio>;
|
||||
sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>;
|
||||
atmel,fifo-size = <16>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -226,8 +232,11 @@
|
|||
|
||||
i2c1: i2c@fc028000 {
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PC7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
at24@50 {
|
||||
|
|
@ -244,18 +253,36 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_flx0_gpio: flx0_gpio {
|
||||
pinmux = <PIN_PB28__GPIO>,
|
||||
<PIN_PB29__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c0_default: i2c0_default {
|
||||
pinmux = <PIN_PD21__TWD0>,
|
||||
<PIN_PD22__TWCK0>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0_gpio {
|
||||
pinmux = <PIN_PD21__GPIO>,
|
||||
<PIN_PD22__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1_default {
|
||||
pinmux = <PIN_PC6__TWD1>,
|
||||
<PIN_PC7__TWCK1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1_gpio {
|
||||
pinmux = <PIN_PC6__GPIO>,
|
||||
<PIN_PC7__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_key_gpio_default: key_gpio_default {
|
||||
pinmux = <PIN_PA10__GPIO>;
|
||||
bias-pull-up;
|
||||
|
|
|
|||
|
|
@ -129,8 +129,11 @@
|
|||
|
||||
i2c0: i2c@f8028000 {
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
|
||||
i2c-sda-hold-time-ns = <350>;
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -331,8 +334,11 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_flx4_default>;
|
||||
pinctrl-1 = <&pinctrl_flx4_gpio>;
|
||||
sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
|
||||
atmel,fifo-size = <16>;
|
||||
i2c-analog-filter;
|
||||
i2c-digital-filter;
|
||||
|
|
@ -343,11 +349,14 @@
|
|||
|
||||
i2c1: i2c@fc028000 {
|
||||
dmas = <0>, <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
i2c-analog-filter;
|
||||
i2c-digital-filter;
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
|
||||
scl-gpios = <&pioA PIN_PD5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
at24@54 {
|
||||
|
|
@ -441,18 +450,36 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_flx4_gpio: flx4_gpio {
|
||||
pinmux = <PIN_PD12__GPIO>,
|
||||
<PIN_PD13__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c0_default: i2c0_default {
|
||||
pinmux = <PIN_PD21__TWD0>,
|
||||
<PIN_PD22__TWCK0>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0_gpio {
|
||||
pinmux = <PIN_PD21__GPIO>,
|
||||
<PIN_PD22__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1_default {
|
||||
pinmux = <PIN_PD4__TWD1>,
|
||||
<PIN_PD5__TWCK1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1_gpio {
|
||||
pinmux = <PIN_PD4__GPIO>,
|
||||
<PIN_PD5__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_i2s0_default: i2s0_default {
|
||||
pinmux = <PIN_PC1__I2SC0_CK>,
|
||||
<PIN_PC2__I2SC0_MCK>,
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@
|
|||
|
||||
panel: panel {
|
||||
/* Actually Ampire 800480R2 */
|
||||
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
|
||||
compatible = "foxlink,fl500wvr00-a0t";
|
||||
backlight = <&backlight>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -238,7 +238,7 @@
|
|||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "qiaodian,qd43003c0-40", "simple-panel";
|
||||
compatible = "qiaodian,qd43003c0-40";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&panel_reg>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
|
||||
compatible = "foxlink,fl500wvr00-a0t";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&panel_reg>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
};
|
||||
|
||||
aliases {
|
||||
emmc2bus = &emmc2bus;
|
||||
ethernet0 = &genet;
|
||||
pcie0 = &pcie0;
|
||||
};
|
||||
|
|
@ -74,6 +75,79 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/*
|
||||
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
|
||||
* the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
gpio-line-names = "ID_SDA",
|
||||
"ID_SCL",
|
||||
"SDA1",
|
||||
"SCL1",
|
||||
"GPIO_GCLK",
|
||||
"GPIO5",
|
||||
"GPIO6",
|
||||
"SPI_CE1_N",
|
||||
"SPI_CE0_N",
|
||||
"SPI_MISO",
|
||||
"SPI_MOSI",
|
||||
"SPI_SCLK",
|
||||
"GPIO12",
|
||||
"GPIO13",
|
||||
/* Serial port */
|
||||
"TXD1",
|
||||
"RXD1",
|
||||
"GPIO16",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"GPIO19",
|
||||
"GPIO20",
|
||||
"GPIO21",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"GPIO26",
|
||||
"GPIO27",
|
||||
"RGMII_MDIO",
|
||||
"RGMIO_MDC",
|
||||
/* Used by BT module */
|
||||
"CTS0",
|
||||
"RTS0",
|
||||
"TXD0",
|
||||
"RXD0",
|
||||
/* Used by Wifi */
|
||||
"SD1_CLK",
|
||||
"SD1_CMD",
|
||||
"SD1_DATA0",
|
||||
"SD1_DATA1",
|
||||
"SD1_DATA2",
|
||||
"SD1_DATA3",
|
||||
/* Shared with SPI flash */
|
||||
"PWM0_MISO",
|
||||
"PWM1_MOSI",
|
||||
"STATUS_LED_G_CLK",
|
||||
"SPIFLASH_CE_N",
|
||||
"SDA0",
|
||||
"SCL0",
|
||||
"RGMII_RXCLK",
|
||||
"RGMII_RXCTL",
|
||||
"RGMII_RXD0",
|
||||
"RGMII_RXD1",
|
||||
"RGMII_RXD2",
|
||||
"RGMII_RXD3",
|
||||
"RGMII_TXCLK",
|
||||
"RGMII_TXCTL",
|
||||
"RGMII_TXD0",
|
||||
"RGMII_TXD1",
|
||||
"RGMII_TXD2",
|
||||
"RGMII_TXD3";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
|
||||
|
|
|
|||
|
|
@ -241,17 +241,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hvs@7e400000 {
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* emmc2 has different DMA constraints based on SoC revisions. It was
|
||||
* moved into its own bus, so as for RPi4's firmware to update them.
|
||||
* The firmware will find whether the emmc2bus alias is defined, and if
|
||||
* so, it'll edit the dma-ranges property below accordingly.
|
||||
*/
|
||||
emmc2bus: emmc2bus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
|
||||
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
|
||||
|
||||
emmc2: emmc2@7e340000 {
|
||||
compatible = "brcm,bcm2711-emmc2";
|
||||
reg = <0x7e340000 0x100>;
|
||||
reg = <0x0 0x7e340000 0x100>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clocks BCM2711_CLOCK_EMMC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hvs@7e400000 {
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
|
|
|
|||
|
|
@ -362,4 +362,18 @@
|
|||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x15d4 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x15d4 0x4>;
|
||||
|
||||
alwon_ethernet_clkctrl: clk@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
#include <dt-bindings/clock/dm814.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/dm814x.h>
|
||||
|
||||
|
|
@ -519,53 +521,123 @@
|
|||
reg = <0x47810000 0x1000>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
ti,hwmods = "tpcc";
|
||||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
target-module@49000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49000000 0x10000>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 3>, <&edma_tptc3 0>;
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 3>, <&edma_tptc3 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@49800000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc0";
|
||||
reg = <0x49800000 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49800000 0x4>,
|
||||
<0x49800010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49800000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc1: tptc@49900000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc1";
|
||||
reg = <0x49900000 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc2: tptc@49a00000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc2";
|
||||
reg = <0x49a00000 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc3: tptc@49b00000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc3";
|
||||
reg = <0x49b00000 0x100000>;
|
||||
interrupts = <115>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49b00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49b00000 0x4>,
|
||||
<0x49b00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49b00000 0x100000>;
|
||||
|
||||
edma_tptc3: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <115>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
/* See TRM "Table 1-318. L4HS Instance Summary" */
|
||||
|
|
@ -574,57 +646,73 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4a000000 0x1b4040>;
|
||||
};
|
||||
|
||||
/* REVISIT: Move to live under l4hs once driver is fixed */
|
||||
mac: ethernet@4a100000 {
|
||||
compatible = "ti,cpsw";
|
||||
ti,hwmods = "cpgmac0";
|
||||
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
||||
clock-names = "fck", "cpts";
|
||||
cpdma_channels = <8>;
|
||||
ale_entries = <1024>;
|
||||
bd_ram_size = <0x2000>;
|
||||
mac_control = <0x20>;
|
||||
slaves = <2>;
|
||||
active_slave = <0>;
|
||||
cpts_clock_mult = <0x80000000>;
|
||||
cpts_clock_shift = <29>;
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a100900 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
/*
|
||||
* c0_rx_thresh_pend
|
||||
* c0_rx_pend
|
||||
* c0_tx_pend
|
||||
* c0_misc_pend
|
||||
*/
|
||||
interrupts = <40 41 42 43>;
|
||||
ranges;
|
||||
syscon = <&scm_conf>;
|
||||
|
||||
davinci_mdio: mdio@4a100800 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
target-module@100000 {
|
||||
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
||||
reg = <0x100900 0x4>,
|
||||
<0x100908 0x4>,
|
||||
<0x100904 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <0>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
reg = <0x4a100800 0x100>;
|
||||
};
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x100000 0x8000>;
|
||||
|
||||
cpsw_emac0: slave@4a100200 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac: ethernet@0 {
|
||||
compatible = "ti,cpsw";
|
||||
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
||||
clock-names = "fck", "cpts";
|
||||
cpdma_channels = <8>;
|
||||
ale_entries = <1024>;
|
||||
bd_ram_size = <0x2000>;
|
||||
mac_control = <0x20>;
|
||||
slaves = <2>;
|
||||
active_slave = <0>;
|
||||
cpts_clock_mult = <0x80000000>;
|
||||
cpts_clock_shift = <29>;
|
||||
reg = <0 0x800>,
|
||||
<0x900 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* c0_rx_thresh_pend
|
||||
* c0_rx_pend
|
||||
* c0_tx_pend
|
||||
* c0_misc_pend
|
||||
*/
|
||||
interrupts = <40 41 42 43>;
|
||||
ranges = <0 0 0x8000>;
|
||||
syscon = <&scm_conf>;
|
||||
|
||||
};
|
||||
davinci_mdio: mdio@800 {
|
||||
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
|
||||
clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
reg = <0x800 0x100>;
|
||||
};
|
||||
|
||||
cpsw_emac1: slave@4a100300 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
cpsw_emac0: slave@200 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
|
||||
cpsw_emac1: slave@300 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
#include <dt-bindings/clock/dm816.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
|
||||
|
|
@ -138,13 +140,123 @@
|
|||
};
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x40>;
|
||||
interrupts = <12 13 14>;
|
||||
#dma-cells = <1>;
|
||||
target-module@49000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49000000 0x10000>;
|
||||
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 3>, <&edma_tptc3 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49800000 0x4>,
|
||||
<0x49800010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49800000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@49b00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49b00000 0x4>,
|
||||
<0x49b00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49b00000 0x100000>;
|
||||
|
||||
edma_tptc3: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <115>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
|
|
@ -185,7 +297,7 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dmas = <&edma 52 0>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
|
|
@ -202,7 +314,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
dmas = <&edma 58 &edma 59>;
|
||||
dmas = <&edma 58 0 &edma 59 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -213,7 +325,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <71>;
|
||||
dmas = <&edma 60 &edma 61>;
|
||||
dmas = <&edma 60 0 &edma 61 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -311,10 +423,10 @@
|
|||
interrupts = <65>;
|
||||
ti,spi-num-cs = <4>;
|
||||
ti,hwmods = "mcspi1";
|
||||
dmas = <&edma 16 &edma 17
|
||||
&edma 18 &edma 19
|
||||
&edma 20 &edma 21
|
||||
&edma 22 &edma 23>;
|
||||
dmas = <&edma 16 0 &edma 17 0
|
||||
&edma 18 0 &edma 19 0
|
||||
&edma 20 0 &edma 21 0
|
||||
&edma 22 0 &edma 23 0>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1",
|
||||
"tx2", "rx2", "tx3", "rx3";
|
||||
};
|
||||
|
|
@ -324,7 +436,7 @@
|
|||
reg = <0x48060000 0x11000>;
|
||||
ti,hwmods = "mmc1";
|
||||
interrupts = <64>;
|
||||
dmas = <&edma 24 &edma 25>;
|
||||
dmas = <&edma 24 0 &edma 25 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -392,7 +504,7 @@
|
|||
reg = <0x48020000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <72>;
|
||||
dmas = <&edma 26 &edma 27>;
|
||||
dmas = <&edma 26 0 &edma 27 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -402,7 +514,7 @@
|
|||
reg = <0x48022000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <73>;
|
||||
dmas = <&edma 28 &edma 29>;
|
||||
dmas = <&edma 28 0 &edma 29 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -412,7 +524,7 @@
|
|||
reg = <0x48024000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <74>;
|
||||
dmas = <&edma 30 &edma 31>;
|
||||
dmas = <&edma 30 0 &edma 31 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,12 +12,12 @@
|
|||
|
||||
/* Compared to dm814x, dra62x has different offsets for Ethernet */
|
||||
&mac {
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a101200 0x100>;
|
||||
reg = <0 0x800>,
|
||||
<0x1200 0x100>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
reg = <0x4a101000 0x100>;
|
||||
reg = <0x1000 0x100>;
|
||||
};
|
||||
|
||||
#include "dra62x-clocks.dtsi"
|
||||
|
|
|
|||
|
|
@ -143,7 +143,7 @@
|
|||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
ocp: ocp {
|
||||
compatible = "ti,dra7-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -334,43 +334,73 @@
|
|||
#pinctrl-cells = <2>;
|
||||
};
|
||||
|
||||
edma: edma@43300000 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
ti,hwmods = "tpcc";
|
||||
reg = <0x43300000 0x100000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
target-module@43300000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43300000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x43300000 0x100000>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x100000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
/*
|
||||
* memcpy is disabled, can be enabled with:
|
||||
* ti,edma-memcpy-channels = <20 21>;
|
||||
* for example. Note that these channels need to be
|
||||
* masked in the xbar as well.
|
||||
*/
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
|
||||
|
||||
/*
|
||||
* memcpy is disabled, can be enabled with:
|
||||
* ti,edma-memcpy-channels = <20 21>;
|
||||
* for example. Note that these channels need to be
|
||||
* masked in the xbar as well.
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@43400000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc0";
|
||||
reg = <0x43400000 0x100000>;
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@43400000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43400000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x43400000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc1: tptc@43500000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc1";
|
||||
reg = <0x43500000 0x100000>;
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@43500000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x43500000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x43500000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
dmm@4e000000 {
|
||||
|
|
@ -708,44 +738,99 @@
|
|||
ti,irqs-safe-map = <0>;
|
||||
};
|
||||
|
||||
dss: dss@58000000 {
|
||||
compatible = "ti,dra7-dss";
|
||||
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
|
||||
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_core";
|
||||
/* CTRL_CORE_DSS_PLL_CONTROL */
|
||||
syscon-pll-ctrl = <&scm_conf 0x538>;
|
||||
target-module@58000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x58000000 4>,
|
||||
<0x58000014 4>;
|
||||
reg-names = "rev", "syss";
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
|
||||
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
|
||||
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
|
||||
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0 0x58000000 0x800000>;
|
||||
|
||||
dispc@58001000 {
|
||||
compatible = "ti,dra7-dispc";
|
||||
reg = <0x58001000 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
/* CTRL_CORE_SMA_SW_1 */
|
||||
syscon-pol = <&scm_conf 0x534>;
|
||||
};
|
||||
|
||||
hdmi: encoder@58060000 {
|
||||
compatible = "ti,dra7-hdmi";
|
||||
reg = <0x58040000 0x200>,
|
||||
<0x58040200 0x80>,
|
||||
<0x58040300 0x80>,
|
||||
<0x58060000 0x19000>;
|
||||
reg-names = "wp", "pll", "phy", "core";
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dss: dss@0 {
|
||||
compatible = "ti,dra7-dss";
|
||||
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
|
||||
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_hdmi";
|
||||
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
dmas = <&sdma_xbar 76>;
|
||||
dma-names = "audio_tx";
|
||||
/* CTRL_CORE_DSS_PLL_CONTROL */
|
||||
syscon-pll-ctrl = <&scm_conf 0x538>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x800000>;
|
||||
|
||||
target-module@1000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x1000 0x4>,
|
||||
<0x1010 0x4>,
|
||||
<0x1014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x1000>;
|
||||
|
||||
dispc@0 {
|
||||
compatible = "ti,dra7-dispc";
|
||||
reg = <0 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
/* CTRL_CORE_SMA_SW_1 */
|
||||
syscon-pol = <&scm_conf 0x534>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@40000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x40000 0x4>,
|
||||
<0x40010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
|
||||
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck", "dss_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40000 0x40000>;
|
||||
|
||||
hdmi: encoder@0 {
|
||||
compatible = "ti,dra7-hdmi";
|
||||
reg = <0 0x200>,
|
||||
<0x200 0x80>,
|
||||
<0x300 0x80>,
|
||||
<0x20000 0x19000>;
|
||||
reg-names = "wp", "pll", "phy", "core";
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
dmas = <&sdma_xbar 76>;
|
||||
dma-names = "audio_tx";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -60,9 +60,9 @@
|
|||
};
|
||||
|
||||
&dss {
|
||||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
<0x58004300 0x20>;
|
||||
reg = <0 0x80>,
|
||||
<0x4054 0x4>,
|
||||
<0x4300 0x20>;
|
||||
reg-names = "dss", "pll1_clkctrl", "pll1";
|
||||
|
||||
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
|
||||
|
|
|
|||
|
|
@ -132,11 +132,11 @@
|
|||
};
|
||||
|
||||
&dss {
|
||||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
<0x58004300 0x20>,
|
||||
<0x58009054 0x4>,
|
||||
<0x58009300 0x20>;
|
||||
reg = <0 0x80>,
|
||||
<0x4054 0x4>,
|
||||
<0x4300 0x20>,
|
||||
<0x9054 0x4>,
|
||||
<0x9300 0x20>;
|
||||
reg-names = "dss", "pll1_clkctrl", "pll1",
|
||||
"pll2_clkctrl", "pll2";
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
compatible = "calxeda,ecx-2000";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
clock-ranges;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -83,8 +82,7 @@
|
|||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 9 0xf04>;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
|
|
@ -95,7 +93,7 @@
|
|||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
|
||||
interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,10 +27,11 @@
|
|||
reg = <0xffe08000 0x10000>;
|
||||
interrupts = <0 83 4>;
|
||||
dma-coherent;
|
||||
calxeda,port-phys = <&combophy5 0 &combophy0 0
|
||||
&combophy0 1 &combophy0 2
|
||||
&combophy0 3>;
|
||||
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
|
||||
calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
|
||||
<&combophy0 1>, <&combophy0 2>,
|
||||
<&combophy0 3>;
|
||||
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
|
||||
<&gpioh 7 1>;
|
||||
calxeda,led-order = <4 0 1 2 3>;
|
||||
};
|
||||
|
||||
|
|
@ -114,8 +115,8 @@
|
|||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xfff36000 0x1000>;
|
||||
interrupts = <0 20 4>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
clocks = <&pclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
smic@fff3a000 {
|
||||
|
|
@ -202,14 +203,14 @@
|
|||
ethernet@fff50000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff50000 0x1000>;
|
||||
interrupts = <0 77 4 0 78 4 0 79 4>;
|
||||
interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
ethernet@fff51000 {
|
||||
compatible = "calxeda,hb-xgmac";
|
||||
reg = <0xfff51000 0x1000>;
|
||||
interrupts = <0 80 4 0 81 4 0 82 4>;
|
||||
interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x1ff00000>;
|
||||
reg = <0x40000000 0x1f800000>;
|
||||
};
|
||||
|
||||
firmware@205f000 {
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@
|
|||
gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>;
|
||||
gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>;
|
||||
cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
lcd@0 {
|
||||
compatible = "samsung,ld9040";
|
||||
|
|
@ -124,8 +124,6 @@
|
|||
vci-supply = <&ldo17_reg>;
|
||||
reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
|
||||
spi-max-frequency = <1200000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
power-on-delay = <10>;
|
||||
reset-delay = <10>;
|
||||
panel-width-mm = <90>;
|
||||
|
|
|
|||
|
|
@ -165,6 +165,15 @@
|
|||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
opp-1000000000 {
|
||||
opp-suspend;
|
||||
};
|
||||
opp-800000000 {
|
||||
/delete-property/opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
gpio_power_key: power_key {
|
||||
samsung,pins = "gpx1-3";
|
||||
|
|
|
|||
|
|
@ -93,22 +93,23 @@
|
|||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "MAIN_DC";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mmc_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "VDD_33ON_2.8V";
|
||||
regulator-name = "VDD_MMC";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_hdmi_en: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "hdmi-en";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_1v2_reg: regulator@3 {
|
||||
|
|
@ -117,6 +118,7 @@
|
|||
regulator-name = "VCC_1V2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_1v8_reg: regulator@4 {
|
||||
|
|
@ -125,6 +127,7 @@
|
|||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3_reg: regulator@5 {
|
||||
|
|
@ -133,6 +136,7 @@
|
|||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -584,6 +584,7 @@
|
|||
regulator-name = "PVDD_G3DS_1V0";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -697,6 +698,7 @@
|
|||
regulator-name = "PVDD_G3D_1V0";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <539>;
|
||||
dynamic-power-coefficient = <90>;
|
||||
};
|
||||
|
||||
cpu1: cpu@101 {
|
||||
|
|
@ -43,6 +44,7 @@
|
|||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <539>;
|
||||
dynamic-power-coefficient = <90>;
|
||||
};
|
||||
|
||||
cpu2: cpu@102 {
|
||||
|
|
@ -55,6 +57,7 @@
|
|||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <539>;
|
||||
dynamic-power-coefficient = <90>;
|
||||
};
|
||||
|
||||
cpu3: cpu@103 {
|
||||
|
|
@ -67,6 +70,7 @@
|
|||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <539>;
|
||||
dynamic-power-coefficient = <90>;
|
||||
};
|
||||
|
||||
cpu4: cpu@0 {
|
||||
|
|
@ -79,6 +83,7 @@
|
|||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <310>;
|
||||
};
|
||||
|
||||
cpu5: cpu@1 {
|
||||
|
|
@ -91,6 +96,7 @@
|
|||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <310>;
|
||||
};
|
||||
|
||||
cpu6: cpu@2 {
|
||||
|
|
@ -103,6 +109,7 @@
|
|||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <310>;
|
||||
};
|
||||
|
||||
cpu7: cpu@3 {
|
||||
|
|
@ -115,6 +122,7 @@
|
|||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <310>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -901,6 +901,7 @@
|
|||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
|
|
|
|||
|
|
@ -215,6 +215,36 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
gpu_thermal: gpu-thermal {
|
||||
thermal-sensors = <&tmu_gpu 0>;
|
||||
trips {
|
||||
gpu_alert0: gpu-alert-0 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <10000>;
|
||||
type = "active";
|
||||
};
|
||||
gpu_alert1: gpu-alert-1 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <10000>;
|
||||
type = "active";
|
||||
};
|
||||
gpu_crit0: gpu-crit-0 {
|
||||
temperature = <120000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpu_alert0>;
|
||||
cooling-device = <&gpu 0 2>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&gpu_alert1>;
|
||||
cooling-device = <&gpu 3 6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -357,6 +357,65 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
gpu_thermal: gpu-thermal {
|
||||
thermal-sensors = <&tmu_gpu 0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
gpu_alert0: gpu-alert-0 {
|
||||
temperature = <50000>;
|
||||
hysteresis = <5000>;
|
||||
type = "active";
|
||||
};
|
||||
gpu_alert1: gpu-alert-1 {
|
||||
temperature = <60000>;
|
||||
hysteresis = <5000>;
|
||||
type = "active";
|
||||
};
|
||||
gpu_alert2: gpu-alert-2 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <5000>;
|
||||
type = "active";
|
||||
};
|
||||
gpu_crit0: gpu-crit-0 {
|
||||
temperature = <120000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
gpu_alert3: gpu-alert-3 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
gpu_alert4: gpu-alert-4 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpu_alert0>;
|
||||
cooling-device = <&fan0 0 1>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&gpu_alert1>;
|
||||
cooling-device = <&fan0 1 2>;
|
||||
};
|
||||
map2 {
|
||||
trip = <&gpu_alert2>;
|
||||
cooling-device = <&fan0 2 3>;
|
||||
};
|
||||
map3 {
|
||||
trip = <&gpu_alert3>;
|
||||
cooling-device = <&gpu 0 2>;
|
||||
};
|
||||
map4 {
|
||||
trip = <&gpu_alert4>;
|
||||
cooling-device = <&gpu 3 6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -119,13 +119,11 @@
|
|||
|
||||
/*
|
||||
* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
|
||||
* Since the platform has no temperature sensor, this is controlled
|
||||
* from userspace by using the hard disks S.M.A.R.T. temperature
|
||||
* sensor. It is turned on when the temperature exceeds 46 degrees
|
||||
* and turned off when the temperatures goes below 41 degrees
|
||||
* (celsius).
|
||||
*/
|
||||
gpio-fan {
|
||||
fan0: gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
/* Collides with IDE */
|
||||
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
|
|
@ -133,6 +131,40 @@
|
|||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
chassis-thermal {
|
||||
/* Poll every 20 seconds */
|
||||
polling-delay = <20000>;
|
||||
/* Poll every 2nd second when cooling */
|
||||
polling-delay-passive = <2000>;
|
||||
/* Use the thermal sensor in the hard drive */
|
||||
thermal-sensors = <&drive0>;
|
||||
|
||||
/* Tripping points from the fan.script in the rootfs */
|
||||
trips {
|
||||
alert: chassis-alert {
|
||||
/* At 43 degrees turn on the fan */
|
||||
temperature = <43000>;
|
||||
hysteresis = <3000>;
|
||||
type = "active";
|
||||
};
|
||||
crit: chassis-crit {
|
||||
/* Just shut down at 60 degrees */
|
||||
temperature = <60000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert>;
|
||||
cooling-device = <&fan0 1 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The touchpad input is connected to a GPIO bit-banged
|
||||
* I2C bus.
|
||||
|
|
@ -443,8 +475,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* This drive may have a temperature sensor with a
|
||||
* thermal zone we can use for thermal control of the
|
||||
* chassis temperature using the fan.
|
||||
*/
|
||||
drive0: ide-port@0 {
|
||||
reg = <0>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-controller@6a000000 {
|
||||
|
|
|
|||
|
|
@ -297,7 +297,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -170,11 +170,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ata@63400000 {
|
||||
ide@63400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -293,11 +293,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ata@63400000 {
|
||||
ide@63400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -289,7 +289,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -356,7 +356,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
ata@63000000 {
|
||||
ide@63000000 {
|
||||
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
||||
reg = <0x63000000 0x1000>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -365,9 +365,11 @@
|
|||
clock-names = "PCLK";
|
||||
sata = <&sata>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ata@63400000 {
|
||||
ide@63400000 {
|
||||
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
||||
reg = <0x63400000 0x1000>;
|
||||
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -376,6 +378,8 @@
|
|||
clock-names = "PCLK";
|
||||
sata = <&sata>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
dma-controller@67000000 {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
compatible = "calxeda,highbank";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-ranges;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -96,7 +95,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0xff900000>;
|
||||
|
|
@ -128,14 +127,12 @@
|
|||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff10100 0x100>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
L2: cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
interrupts = <0 70 4>;
|
||||
|
|
@ -145,14 +142,14 @@
|
|||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
|
||||
interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
|
||||
};
|
||||
|
||||
|
||||
sregs@fff3c200 {
|
||||
compatible = "calxeda,hb-sregs-l2-ecc";
|
||||
reg = <0xfff3c200 0x100>;
|
||||
interrupts = <0 71 4 0 72 4>;
|
||||
interrupts = <0 71 4>, <0 72 4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
ssp0: spi@80010000 {
|
||||
compatible = "fsl,imx23-mmc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
|
||||
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
|
||||
bus-width = <4>;
|
||||
broken-cd;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -267,6 +267,14 @@
|
|||
fsl,pull-up = <MXS_PULL_DISABLE>;
|
||||
};
|
||||
|
||||
mmc0_sck_cfg: mmc0-sck-cfg@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
MX23_PAD_SSP1_SCK__SSP1_SCK
|
||||
>;
|
||||
fsl,pull-up = <MXS_PULL_DISABLE>;
|
||||
};
|
||||
|
||||
mmc1_4bit_pins_a: mmc1-4bit@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -422,7 +430,7 @@
|
|||
clocks = <&clks 16>;
|
||||
};
|
||||
|
||||
dcp@80028000 {
|
||||
dcp: crypto@80028000 {
|
||||
compatible = "fsl,imx23-dcp";
|
||||
reg = <0x80028000 0x2000>;
|
||||
interrupts = <53 54>;
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@
|
|||
#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000
|
||||
#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000
|
||||
#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000
|
||||
#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000
|
||||
|
||||
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000
|
||||
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000
|
||||
|
|
@ -102,11 +103,13 @@
|
|||
#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
|
||||
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000
|
||||
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000
|
||||
#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000
|
||||
|
||||
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000
|
||||
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
|
||||
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000
|
||||
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000
|
||||
#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000
|
||||
|
||||
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000
|
||||
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000
|
||||
|
|
@ -114,6 +117,7 @@
|
|||
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000
|
||||
#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000
|
||||
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000
|
||||
#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000
|
||||
|
||||
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000
|
||||
#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000
|
||||
|
|
@ -251,10 +255,12 @@
|
|||
|
||||
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
|
||||
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
|
||||
#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000
|
||||
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001
|
||||
|
||||
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000
|
||||
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
|
||||
#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000
|
||||
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000
|
||||
|
||||
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000
|
||||
|
|
@ -512,9 +518,11 @@
|
|||
|
||||
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000
|
||||
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000
|
||||
#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000
|
||||
|
||||
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000
|
||||
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000
|
||||
#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000
|
||||
|
||||
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@
|
|||
interrupt-parent = <&asic>;
|
||||
ranges;
|
||||
|
||||
aips@43f00000 { /* AIPS1 */
|
||||
bus@43f00000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -332,7 +332,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@53f00000 { /* AIPS2 */
|
||||
bus@53f00000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -525,7 +525,7 @@
|
|||
reg = <0x10024600 0x200>;
|
||||
};
|
||||
|
||||
sahara2: sahara@10025000 {
|
||||
sahara2: crypto@10025000 {
|
||||
compatible = "fsl,imx27-sahara";
|
||||
reg = <0x10025000 0x1000>;
|
||||
interrupts = <59>;
|
||||
|
|
|
|||
|
|
@ -183,10 +183,20 @@
|
|||
pinctrl-0 = <&auart2_2pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb1: usb@80090000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -998,7 +998,7 @@
|
|||
clocks = <&clks 26>;
|
||||
};
|
||||
|
||||
dcp: dcp@80028000 {
|
||||
dcp: crypto@80028000 {
|
||||
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
|
||||
reg = <0x80028000 0x2000>;
|
||||
interrupts = <52 53 54>;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@
|
|||
ranges = <0 0x1fffc000 0x4000>;
|
||||
};
|
||||
|
||||
aips@43f00000 { /* AIPS1 */
|
||||
bus@43f00000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -225,7 +225,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@53f00000 { /* AIPS2 */
|
||||
bus@53f00000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@
|
|||
cache-level = <2>;
|
||||
};
|
||||
|
||||
aips1: aips@43f00000 {
|
||||
aips1: bus@43f00000 {
|
||||
compatible = "fsl,aips", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -199,7 +199,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips2: aips@53f00000 {
|
||||
aips2: bus@53f00000 {
|
||||
compatible = "fsl,aips", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@
|
|||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
bus@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -389,7 +389,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
bus@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -217,8 +217,8 @@
|
|||
simple-audio-card,widgets =
|
||||
"Headphone", "Headphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPLEFT",
|
||||
"Headphone Jack", "HPRIGHT";
|
||||
"Headphone Jack", "TPA6130A2 HPLEFT",
|
||||
"Headphone Jack", "TPA6130A2 HPRIGHT";
|
||||
simple-audio-card,aux-devs = <&hpa1>;
|
||||
|
||||
sound_cpu: simple-audio-card,cpu {
|
||||
|
|
@ -470,6 +470,7 @@
|
|||
compatible = "ti,tpa6130a2";
|
||||
reg = <0x60>;
|
||||
Vdd-supply = <®_3p3v>;
|
||||
sound-name-prefix = "TPA6130A2";
|
||||
};
|
||||
|
||||
ds1341: rtc@68 {
|
||||
|
|
|
|||
|
|
@ -104,6 +104,11 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
capture-subsystem {
|
||||
compatible = "fsl,imx-capture-subsystem";
|
||||
ports = <&ipu_csi0>, <&ipu_csi1>;
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>, <&ipu_di1>;
|
||||
|
|
@ -143,6 +148,14 @@
|
|||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu_csi0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_csi1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
ipu_di0: port@2 {
|
||||
reg = <2>;
|
||||
|
||||
|
|
@ -158,7 +171,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@70000000 { /* AIPS1 */
|
||||
bus@70000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -440,7 +453,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* AIPS2 */
|
||||
bus@80000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@
|
|||
clock-names = "core_clk", "mem_iface_clk";
|
||||
};
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
bus@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -654,7 +654,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
bus@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue