perf, x86: Fix AMD family 15h FPU event constraints
Depending on the unit mask settings some FPU events may be scheduled only on cpu counter #3. This patch fixes this. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Stephane Eranian <eranian@googlemail.com> Link: http://lkml.kernel.org/r/1302913676-14352-3-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -427,7 +427,9 @@ static __initconst const struct x86_pmu amd_pmu = {
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*
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* Exceptions:
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*
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* 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
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* 0x003 FP PERF_CTL[3]
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* 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
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* 0x00B FP PERF_CTL[3]
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* 0x00D FP PERF_CTL[3]
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* 0x023 DE PERF_CTL[2:0]
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@ -448,6 +450,8 @@ static __initconst const struct x86_pmu amd_pmu = {
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* 0x0DF LS PERF_CTL[5:0]
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* 0x1D6 EX PERF_CTL[5:0]
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* 0x1D8 EX PERF_CTL[5:0]
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*
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* (*) depending on the umask all FPU counters may be used
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*/
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static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0);
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@ -460,18 +464,28 @@ static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
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static struct event_constraint *
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amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
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{
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unsigned int event_code = amd_get_event_code(&event->hw);
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struct hw_perf_event *hwc = &event->hw;
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unsigned int event_code = amd_get_event_code(hwc);
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switch (event_code & AMD_EVENT_TYPE_MASK) {
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case AMD_EVENT_FP:
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switch (event_code) {
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case 0x000:
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if (!(hwc->config & 0x0000F000ULL))
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break;
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if (!(hwc->config & 0x00000F00ULL))
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break;
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return &amd_f15_PMC3;
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case 0x004:
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if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
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break;
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return &amd_f15_PMC3;
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case 0x003:
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case 0x00B:
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case 0x00D:
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return &amd_f15_PMC3;
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default:
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return &amd_f15_PMC53;
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}
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return &amd_f15_PMC53;
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case AMD_EVENT_LS:
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case AMD_EVENT_DC:
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case AMD_EVENT_EX_LS:
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