ARM: sun5i: a13: Merge common controllers into the common DTSI
Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>hifive-unleashed-5.1
Maxime Ripard
parent
e6f50b223d
commit
8587019625
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@ -52,21 +52,6 @@
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/ {
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interrupt-parent = <&intc>;
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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@ -105,44 +90,6 @@
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};
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soc@01c00000 {
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun5i-a13-pwm";
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reg = <0x01c20e00 0xc>;
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@ -151,74 +98,6 @@
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status = "disabled";
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};
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fe0: display-frontend@01e00000 {
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compatible = "allwinner,sun5i-a13-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <47>;
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clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_DE_FE>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun5i-a13-display-backend";
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reg = <0x01e60000 0x10000>;
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clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_DE_BE>;
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status = "disabled";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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};
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};
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};
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};
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};
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@ -244,22 +123,4 @@
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&pio {
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compatible = "allwinner,sun5i-a13-pinctrl";
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lcd_rgb666_pins: lcd_rgb666@0 {
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pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
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function = "lcd0";
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};
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uart1_pins_a: uart1@0 {
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pins = "PE10", "PE11";
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function = "uart1";
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};
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uart1_pins_b: uart1@1 {
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pins = "PG3", "PG4";
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function = "uart1";
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};
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};
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@ -64,6 +64,21 @@
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};
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
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status = "disabled";
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -156,6 +171,44 @@
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#size-cells = <0>;
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};
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&ccu RST_LCD>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD>,
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<&ccu CLK_TCON_CH0>,
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<&ccu CLK_TCON_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -296,6 +349,14 @@
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function = "lcd0";
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};
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lcd_rgb666_pins: lcd_rgb666@0 {
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pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
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function = "lcd0";
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};
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mmc0_pins_a: mmc0@0 {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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@ -331,6 +392,16 @@
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function = "spi2";
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};
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uart1_pins_a: uart1@0 {
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pins = "PE10", "PE11";
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function = "uart1";
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};
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uart1_pins_b: uart1@1 {
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pins = "PG3", "PG4";
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function = "uart1";
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};
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uart2_pins_a: uart2@0 {
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pins = "PD2", "PD3";
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function = "uart2";
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@ -457,5 +528,74 @@
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interrupts = <82>, <83>;
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clocks = <&ccu CLK_AHB_HSTIMER>;
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};
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fe0: display-frontend@01e00000 {
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compatible = "allwinner,sun5i-a13-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <47>;
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clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_DE_FE>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun5i-a13-display-backend";
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reg = <0x01e60000 0x10000>;
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clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_DE_BE>;
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status = "disabled";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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};
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};
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};
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};
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};
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