V4L/DVB: V4L - vpfe capture - vpss driver enhancements for DM365
Enhancements to support DM365 ISP5 and VPSS module configuration. Also cleaned up the driver by removing redundant variables. Reviewed-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Murali Karicheri <mkaricheri@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>hifive-unleashed-5.1
Murali Karicheri
Mauro Carvalho Chehab
parent
63e3ab142f
commit
85b848caf7
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@ -15,7 +15,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* common vpss driver for all video drivers.
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* common vpss system module platform driver for all video drivers.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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@ -35,12 +35,52 @@ MODULE_AUTHOR("Texas Instruments");
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/* DM644x defines */
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#define DM644X_SBL_PCR_VPSS (4)
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#define DM355_VPSSBL_INTSEL 0x10
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#define DM355_VPSSBL_EVTSEL 0x14
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/* vpss BL register offsets */
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#define DM355_VPSSBL_CCDCMUX 0x1c
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/* vpss CLK register offsets */
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#define DM355_VPSSCLK_CLKCTRL 0x04
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/* masks and shifts */
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#define VPSS_HSSISEL_SHIFT 4
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/*
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* VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
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* IPIPE_INT1_SDR - vpss_int5
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*/
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#define DM355_VPSSBL_INTSEL_DEFAULT 0xff83ff10
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/* VENCINT - vpss_int8 */
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#define DM355_VPSSBL_EVTSEL_DEFAULT 0x4
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#define DM365_ISP5_PCCR 0x04
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#define DM365_ISP5_INTSEL1 0x10
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#define DM365_ISP5_INTSEL2 0x14
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#define DM365_ISP5_INTSEL3 0x18
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#define DM365_ISP5_CCDCMUX 0x20
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#define DM365_ISP5_PG_FRAME_SIZE 0x28
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#define DM365_VPBE_CLK_CTRL 0x00
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/*
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* vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
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* AF - vpss_int3
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*/
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#define DM365_ISP5_INTSEL1_DEFAULT 0x0b1f0100
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/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
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#define DM365_ISP5_INTSEL2_DEFAULT 0x1f0a0f1f
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/* VENC - vpss_int8 */
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#define DM365_ISP5_INTSEL3_DEFAULT 0x00000015
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/* masks and shifts for DM365*/
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#define DM365_CCDC_PG_VD_POL_SHIFT 0
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#define DM365_CCDC_PG_HD_POL_SHIFT 1
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#define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4))
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#define CCD_SRC_SEL_SHIFT 4
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/* Different SoC platforms supported by this driver */
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enum vpss_platform_type {
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DM644X,
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DM355,
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DM365,
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};
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/*
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* vpss operations. Depends on platform. Not all functions are available
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@ -59,13 +99,9 @@ struct vpss_hw_ops {
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/* vpss configuration */
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struct vpss_oper_config {
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__iomem void *vpss_bl_regs_base;
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__iomem void *vpss_regs_base;
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struct resource *r1;
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resource_size_t len1;
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struct resource *r2;
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resource_size_t len2;
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char vpss_name[32];
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__iomem void *vpss_regs_base0;
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__iomem void *vpss_regs_base1;
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enum vpss_platform_type platform;
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spinlock_t vpss_lock;
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struct vpss_hw_ops hw_ops;
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};
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@ -75,22 +111,46 @@ static struct vpss_oper_config oper_cfg;
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/* register access routines */
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static inline u32 bl_regr(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_bl_regs_base + offset);
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return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
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}
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static inline void bl_regw(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_bl_regs_base + offset);
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__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
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}
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static inline u32 vpss_regr(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_regs_base + offset);
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return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
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}
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static inline void vpss_regw(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_regs_base + offset);
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__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
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}
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/* For DM365 only */
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static inline u32 isp5_read(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
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}
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/* For DM365 only */
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static inline void isp5_write(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
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}
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static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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{
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u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
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/* if we are using pattern generator, enable it */
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if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
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temp |= 0x08;
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temp |= (src_sel << CCD_SRC_SEL_SHIFT);
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isp5_write(temp, DM365_ISP5_CCDCMUX);
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}
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static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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@ -101,9 +161,9 @@ static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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{
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if (!oper_cfg.hw_ops.select_ccdc_source)
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return -1;
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return -EINVAL;
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dm355_select_ccdc_source(src_sel);
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oper_cfg.hw_ops.select_ccdc_source(src_sel);
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return 0;
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}
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EXPORT_SYMBOL(vpss_select_ccdc_source);
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@ -114,7 +174,7 @@ static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
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if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
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wbl_sel > VPSS_PCR_CCDC_WBL_O)
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return -1;
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return -EINVAL;
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/* writing a 0 clear the overflow */
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mask = ~(mask << wbl_sel);
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@ -126,7 +186,7 @@ static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
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int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
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{
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if (!oper_cfg.hw_ops.clear_wbl_overflow)
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return -1;
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return -EINVAL;
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return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
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}
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@ -166,7 +226,7 @@ static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
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default:
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printk(KERN_ERR "dm355_enable_clock:"
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" Invalid selector: %d\n", clock_sel);
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return -1;
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return -EINVAL;
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}
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spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
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@ -181,100 +241,221 @@ static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
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return 0;
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}
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static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
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{
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unsigned long flags;
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u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
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u32 (*read)(u32 offset) = isp5_read;
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void(*write)(u32 val, u32 offset) = isp5_write;
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switch (clock_sel) {
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case VPSS_BL_CLOCK:
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break;
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case VPSS_CCDC_CLOCK:
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shift = 1;
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break;
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case VPSS_H3A_CLOCK:
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shift = 2;
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break;
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case VPSS_RSZ_CLOCK:
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shift = 3;
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break;
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case VPSS_IPIPE_CLOCK:
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shift = 4;
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break;
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case VPSS_IPIPEIF_CLOCK:
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shift = 5;
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break;
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case VPSS_PCLK_INTERNAL:
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shift = 6;
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break;
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case VPSS_PSYNC_CLOCK_SEL:
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shift = 7;
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break;
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case VPSS_VPBE_CLOCK:
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_VENC_CLOCK_SEL:
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shift = 2;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_LDC_CLOCK:
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shift = 3;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_FDIF_CLOCK:
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shift = 4;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_OSD_CLOCK_SEL:
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shift = 6;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_LDC_CLOCK_SEL:
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shift = 7;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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default:
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printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
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clock_sel);
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return -1;
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}
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spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
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utemp = read(offset);
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if (!en) {
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mask = ~mask;
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utemp &= (mask << shift);
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} else
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utemp |= (mask << shift);
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write(utemp, offset);
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spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
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return 0;
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}
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int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
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{
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if (!oper_cfg.hw_ops.enable_clock)
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return -1;
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return -EINVAL;
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return oper_cfg.hw_ops.enable_clock(clock_sel, en);
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}
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EXPORT_SYMBOL(vpss_enable_clock);
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void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
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{
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int val = 0;
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val = isp5_read(DM365_ISP5_CCDCMUX);
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val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
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val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
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isp5_write(val, DM365_ISP5_CCDCMUX);
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}
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EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
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void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
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{
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int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
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current_reg |= (frame_size.pplen - 1);
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isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
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}
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EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
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static int __init vpss_probe(struct platform_device *pdev)
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{
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int status, dm355 = 0;
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struct resource *r1, *r2;
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char *platform_name;
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int status;
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if (!pdev->dev.platform_data) {
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dev_err(&pdev->dev, "no platform data\n");
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return -ENOENT;
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}
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strcpy(oper_cfg.vpss_name, pdev->dev.platform_data);
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if (!strcmp(oper_cfg.vpss_name, "dm355_vpss"))
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dm355 = 1;
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else if (strcmp(oper_cfg.vpss_name, "dm644x_vpss")) {
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platform_name = pdev->dev.platform_data;
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if (!strcmp(platform_name, "dm355_vpss"))
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oper_cfg.platform = DM355;
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else if (!strcmp(platform_name, "dm365_vpss"))
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oper_cfg.platform = DM365;
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else if (!strcmp(platform_name, "dm644x_vpss"))
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oper_cfg.platform = DM644X;
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else {
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dev_err(&pdev->dev, "vpss driver not supported on"
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" this platform\n");
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return -ENODEV;
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}
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dev_info(&pdev->dev, "%s vpss probed\n", oper_cfg.vpss_name);
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oper_cfg.r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!oper_cfg.r1)
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dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
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r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r1)
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return -ENOENT;
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oper_cfg.len1 = oper_cfg.r1->end - oper_cfg.r1->start + 1;
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oper_cfg.r1 = request_mem_region(oper_cfg.r1->start, oper_cfg.len1,
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oper_cfg.r1->name);
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if (!oper_cfg.r1)
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r1 = request_mem_region(r1->start, resource_size(r1), r1->name);
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if (!r1)
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return -EBUSY;
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oper_cfg.vpss_bl_regs_base = ioremap(oper_cfg.r1->start, oper_cfg.len1);
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if (!oper_cfg.vpss_bl_regs_base) {
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oper_cfg.vpss_regs_base0 = ioremap(r1->start, resource_size(r1));
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if (!oper_cfg.vpss_regs_base0) {
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status = -EBUSY;
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goto fail1;
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}
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if (dm355) {
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oper_cfg.r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!oper_cfg.r2) {
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if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
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r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!r2) {
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status = -ENOENT;
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goto fail2;
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}
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oper_cfg.len2 = oper_cfg.r2->end - oper_cfg.r2->start + 1;
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oper_cfg.r2 = request_mem_region(oper_cfg.r2->start,
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oper_cfg.len2,
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oper_cfg.r2->name);
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if (!oper_cfg.r2) {
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r2 = request_mem_region(r2->start, resource_size(r2), r2->name);
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if (!r2) {
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status = -EBUSY;
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goto fail2;
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}
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oper_cfg.vpss_regs_base = ioremap(oper_cfg.r2->start,
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oper_cfg.len2);
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if (!oper_cfg.vpss_regs_base) {
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oper_cfg.vpss_regs_base1 = ioremap(r2->start,
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resource_size(r2));
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if (!oper_cfg.vpss_regs_base1) {
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status = -EBUSY;
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goto fail3;
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}
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}
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if (dm355) {
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if (oper_cfg.platform == DM355) {
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oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
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oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
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/* Setup vpss interrupts */
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bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
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bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
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} else if (oper_cfg.platform == DM365) {
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oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
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oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
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/* Setup vpss interrupts */
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isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
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isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
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isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
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} else
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oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
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spin_lock_init(&oper_cfg.vpss_lock);
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dev_info(&pdev->dev, "%s vpss probe success\n", oper_cfg.vpss_name);
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dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
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return 0;
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fail3:
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release_mem_region(oper_cfg.r2->start, oper_cfg.len2);
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release_mem_region(r2->start, resource_size(r2));
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fail2:
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iounmap(oper_cfg.vpss_bl_regs_base);
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iounmap(oper_cfg.vpss_regs_base0);
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fail1:
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release_mem_region(oper_cfg.r1->start, oper_cfg.len1);
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release_mem_region(r1->start, resource_size(r1));
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return status;
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}
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static int __devexit vpss_remove(struct platform_device *pdev)
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{
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iounmap(oper_cfg.vpss_bl_regs_base);
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release_mem_region(oper_cfg.r1->start, oper_cfg.len1);
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if (!strcmp(oper_cfg.vpss_name, "dm355_vpss")) {
|
||||
iounmap(oper_cfg.vpss_regs_base);
|
||||
release_mem_region(oper_cfg.r2->start, oper_cfg.len2);
|
||||
struct resource *res;
|
||||
|
||||
iounmap(oper_cfg.vpss_regs_base0);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
|
||||
iounmap(oper_cfg.vpss_regs_base1);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,7 +29,19 @@
|
|||
/* selector for ccdc input selection on DM355 */
|
||||
enum vpss_ccdc_source_sel {
|
||||
VPSS_CCDCIN,
|
||||
VPSS_HSSIIN
|
||||
VPSS_HSSIIN,
|
||||
VPSS_PGLPBK, /* for DM365 only */
|
||||
VPSS_CCDCPG /* for DM365 only */
|
||||
};
|
||||
|
||||
struct vpss_sync_pol {
|
||||
unsigned int ccdpg_hdpol:1;
|
||||
unsigned int ccdpg_vdpol:1;
|
||||
};
|
||||
|
||||
struct vpss_pg_frame_size {
|
||||
short hlpfr;
|
||||
short pplen;
|
||||
};
|
||||
|
||||
/* Used for enable/diable VPSS Clock */
|
||||
|
|
@ -47,12 +59,38 @@ enum vpss_clock_sel {
|
|||
*/
|
||||
VPSS_VENC_CLOCK_SEL,
|
||||
VPSS_VPBE_CLOCK,
|
||||
/* DM365 only clocks */
|
||||
VPSS_IPIPEIF_CLOCK,
|
||||
VPSS_RSZ_CLOCK,
|
||||
VPSS_BL_CLOCK,
|
||||
/*
|
||||
* When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
|
||||
* following applies:-
|
||||
* en = 0 disable internal PCLK
|
||||
* en = 1 enables internal PCLK
|
||||
*/
|
||||
VPSS_PCLK_INTERNAL,
|
||||
/*
|
||||
* When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
|
||||
* following applies:-
|
||||
* en = 0 enables MMR clock
|
||||
* en = 1 enables VPSS clock
|
||||
*/
|
||||
VPSS_PSYNC_CLOCK_SEL,
|
||||
VPSS_LDC_CLOCK_SEL,
|
||||
VPSS_OSD_CLOCK_SEL,
|
||||
VPSS_FDIF_CLOCK,
|
||||
VPSS_LDC_CLOCK
|
||||
};
|
||||
|
||||
/* select input to ccdc on dm355 */
|
||||
int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
|
||||
/* enable/disable a vpss clock, 0 - success, -1 - failure */
|
||||
int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
|
||||
/* set sync polarity, only for DM365*/
|
||||
void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
|
||||
/* set the PG_FRAME_SIZE register, only for DM365 */
|
||||
void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
|
||||
|
||||
/* wbl reset for dm644x */
|
||||
enum vpss_wbl_sel {
|
||||
|
|
@ -65,5 +103,6 @@ enum vpss_wbl_sel {
|
|||
VPSS_PCR_PREV_WBL_0,
|
||||
VPSS_PCR_CCDC_WBL_O,
|
||||
};
|
||||
/* clear wbl overflow flag for DM6446 */
|
||||
int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue