MIPS: lantiq: Add SMP support for lantiq interrupt controller
Some lantiq devices have two ICU controllers. The IRQ signal is routed to both of them and user can chose which ICU will resend the IRQ to their respective VPE. The patch adds the support for the second ICU. The patch changes a register definition of the driver. Instead of an individual IM, the whole ICU is defined. This will only affects openwrt patched kernel (vanilla doesn't have additional .dts files). Also spinlocks has been added, both cores can RMW different bitfields in the same register. Added affinity set function. The new VPE cpumask will take into the action at the irq enable. The functionality was tested on 4.14 openwrt kernel and TP-W9980B modem. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: hauke@hauke-m.de Cc: john@phrozen.org Cc: linux-mips@vger.kernel.org Cc: openwrt-devel@lists.openwrt.org Cc: pakahmar@hotmail.comalistair/sunxi64-5.4-dsi
Petr Cvek
Paul Burton
parent
f0dd300101
commit
85cf2c37cb
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@ -28,6 +28,8 @@
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#define LTQ_ICU_IRSR 0x0018
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#define LTQ_ICU_IMR 0x0020
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#define LTQ_ICU_IM_SIZE 0x28
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/* register definitions - external irqs */
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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@ -46,8 +48,11 @@
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*/
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#define LTQ_ICU_EBU_IRQ 22
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#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
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#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
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#define ltq_icu_w32(vpe, m, x, y) \
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ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
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#define ltq_icu_r32(vpe, m, x) \
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ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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@ -57,9 +62,11 @@
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static int exin_avail;
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static u32 ltq_eiu_irq[MAX_EIU];
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static void __iomem *ltq_icu_membase[MAX_IM];
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static void __iomem *ltq_icu_membase[NR_CPUS];
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static void __iomem *ltq_eiu_membase;
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static struct irq_domain *ltq_domain;
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static DEFINE_SPINLOCK(ltq_eiu_lock);
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static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
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static int ltq_perfcount_irq;
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int ltq_eiu_get_irq(int exin)
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@ -73,45 +80,82 @@ void ltq_disable_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im,
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ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR);
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im,
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ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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static void ltq_ack_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR);
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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void ltq_enable_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) | BIT(offset),
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vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
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/* This shouldn't be even possible, maybe during CPU hotplug spam */
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if (unlikely(vpe >= nr_cpu_ids))
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vpe = smp_processor_id();
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
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LTQ_ICU_IER);
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
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{
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int i;
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unsigned long flags;
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for (i = 0; i < exin_avail; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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@ -148,9 +192,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
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if (edge)
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irq_set_handler(d->hwirq, handle_edge_irq);
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spin_lock_irqsave(<q_eiu_lock, flags);
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ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
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(~(7 << (i * 4)))) | (val << (i * 4)),
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LTQ_EIU_EXIN_C);
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spin_unlock_irqrestore(<q_eiu_lock, flags);
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}
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}
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@ -194,6 +240,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
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}
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}
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#if defined(CONFIG_SMP)
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static int ltq_icu_irq_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask, bool force)
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{
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struct cpumask tmask;
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if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
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return -EINVAL;
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irq_data_update_effective_affinity(d, &tmask);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip ltq_irq_type = {
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.name = "icu",
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.irq_enable = ltq_enable_irq,
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@ -202,6 +263,9 @@ static struct irq_chip ltq_irq_type = {
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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#if defined(CONFIG_SMP)
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.irq_set_affinity = ltq_icu_irq_set_affinity,
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#endif
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};
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static struct irq_chip ltq_eiu_type = {
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@ -215,6 +279,9 @@ static struct irq_chip ltq_eiu_type = {
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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.irq_set_type = ltq_eiu_settype,
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#if defined(CONFIG_SMP)
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.irq_set_affinity = ltq_icu_irq_set_affinity,
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#endif
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};
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static void ltq_hw_irq_handler(struct irq_desc *desc)
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@ -222,8 +289,9 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
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unsigned int module = irq_desc_get_irq(desc) - 2;
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u32 irq;
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irq_hw_number_t hwirq;
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int vpe = smp_processor_id();
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irq = ltq_icu_r32(module, LTQ_ICU_IOSR);
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irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
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if (irq == 0)
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return;
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@ -244,6 +312,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
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static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct irq_chip *chip = <q_irq_type;
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struct irq_data *data;
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int i;
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if (hw < MIPS_CPU_IRQ_CASCADE)
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@ -253,6 +322,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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if (hw == ltq_eiu_irq[i])
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chip = <q_eiu_type;
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data = irq_get_irq_data(irq);
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irq_data_update_effective_affinity(data, cpumask_of(0));
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irq_set_chip_and_handler(irq, chip, handle_level_irq);
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return 0;
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@ -267,28 +340,37 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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{
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struct device_node *eiu_node;
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struct resource res;
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int i, ret;
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int i, ret, vpe;
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for (i = 0; i < MAX_IM; i++) {
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if (of_address_to_resource(node, i, &res))
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panic("Failed to get icu memory range");
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/* load register regions of available ICUs */
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for_each_possible_cpu(vpe) {
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if (of_address_to_resource(node, vpe, &res))
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panic("Failed to get icu%i memory range", vpe);
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if (!request_mem_region(res.start, resource_size(&res),
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res.name))
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pr_err("Failed to request icu memory");
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pr_err("Failed to request icu%i memory\n", vpe);
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ltq_icu_membase[i] = ioremap_nocache(res.start,
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ltq_icu_membase[vpe] = ioremap_nocache(res.start,
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resource_size(&res));
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if (!ltq_icu_membase[i])
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panic("Failed to remap icu memory");
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if (!ltq_icu_membase[vpe])
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panic("Failed to remap icu%i memory", vpe);
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}
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/* turn off all irqs by default */
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for (i = 0; i < MAX_IM; i++) {
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/* make sure all irqs are turned off by default */
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ltq_icu_w32(i, 0, LTQ_ICU_IER);
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/* clear all possibly pending interrupts */
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ltq_icu_w32(i, ~0, LTQ_ICU_ISR);
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for_each_possible_cpu(vpe) {
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for (i = 0; i < MAX_IM; i++) {
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/* make sure all irqs are turned off by default */
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ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
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/* clear all possibly pending interrupts */
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ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
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ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
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/* clear resend */
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ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
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}
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}
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mips_cpu_irq_init();
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