watchdog: Convert jz4740_wdt driver to watchdog core
This patch converts jz4740_wdt driver to use watchdog core APIs. Also use devm_* APIs to save a few error handling code. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>hifive-unleashed-5.1
Axel Lin
Wim Van Sebroeck
parent
86a1e1896c
commit
85f6df1492
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@ -955,6 +955,7 @@ config INDYDOG
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config JZ4740_WDT
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tristate "Ingenic jz4740 SoC hardware watchdog"
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depends on MACH_JZ4740
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select WATCHDOG_CORE
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help
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Hardware driver for the built-in watchdog timer on Ingenic jz4740 SoCs.
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@ -17,18 +17,15 @@
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <asm/mach-jz4740/timer.h>
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@ -41,9 +38,6 @@
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#define JZ_WDT_CLOCK_RTC 0x2
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#define JZ_WDT_CLOCK_EXT 0x4
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#define WDT_IN_USE 0
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#define WDT_OK_TO_CLOSE 1
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#define JZ_WDT_CLOCK_DIV_SHIFT 3
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#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
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@ -56,32 +50,44 @@
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#define DEFAULT_HEARTBEAT 5
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#define MAX_HEARTBEAT 2048
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static struct {
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned int heartbeat = DEFAULT_HEARTBEAT;
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module_param(heartbeat, uint, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat period in seconds from 1 to "
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__MODULE_STRING(MAX_HEARTBEAT) ", default "
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__MODULE_STRING(DEFAULT_HEARTBEAT));
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struct jz4740_wdt_drvdata {
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struct watchdog_device wdt;
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void __iomem *base;
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struct resource *mem;
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struct clk *rtc_clk;
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unsigned long status;
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} jz4740_wdt;
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};
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static int heartbeat = DEFAULT_HEARTBEAT;
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static void jz4740_wdt_service(void)
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static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
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{
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writew(0x0, jz4740_wdt.base + JZ_REG_WDT_TIMER_COUNTER);
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
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return 0;
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}
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static void jz4740_wdt_set_heartbeat(int new_heartbeat)
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static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
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unsigned int new_timeout)
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{
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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unsigned int rtc_clk_rate;
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unsigned int timeout_value;
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unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
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heartbeat = new_heartbeat;
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rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
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rtc_clk_rate = clk_get_rate(jz4740_wdt.rtc_clk);
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timeout_value = rtc_clk_rate * heartbeat;
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timeout_value = rtc_clk_rate * new_timeout;
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while (timeout_value > 0xffff) {
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if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
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/* Requested timeout too high;
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@ -93,199 +99,114 @@ static void jz4740_wdt_set_heartbeat(int new_heartbeat)
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clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
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}
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writeb(0x0, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE);
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writew(clock_div, jz4740_wdt.base + JZ_REG_WDT_TIMER_CONTROL);
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writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
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writew((u16)timeout_value, jz4740_wdt.base + JZ_REG_WDT_TIMER_DATA);
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writew(0x0, jz4740_wdt.base + JZ_REG_WDT_TIMER_COUNTER);
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writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
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writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
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writew(clock_div | JZ_WDT_CLOCK_RTC,
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jz4740_wdt.base + JZ_REG_WDT_TIMER_CONTROL);
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drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
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writeb(0x1, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE);
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}
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writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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static void jz4740_wdt_enable(void)
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{
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jz4740_timer_enable_watchdog();
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jz4740_wdt_set_heartbeat(heartbeat);
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}
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static void jz4740_wdt_disable(void)
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{
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jz4740_timer_disable_watchdog();
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writeb(0x0, jz4740_wdt.base + JZ_REG_WDT_COUNTER_ENABLE);
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}
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static int jz4740_wdt_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(WDT_IN_USE, &jz4740_wdt.status))
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return -EBUSY;
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jz4740_wdt_enable();
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return nonseekable_open(inode, file);
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}
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static ssize_t jz4740_wdt_write(struct file *file, const char *data,
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size_t len, loff_t *ppos)
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{
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if (len) {
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size_t i;
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clear_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status);
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for (i = 0; i != len; i++) {
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char c;
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if (get_user(c, data + i))
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return -EFAULT;
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if (c == 'V')
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set_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status);
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}
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jz4740_wdt_service();
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}
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return len;
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}
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static const struct watchdog_info ident = {
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.options = WDIOF_KEEPALIVEPING,
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.identity = "jz4740 Watchdog",
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};
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static long jz4740_wdt_ioctl(struct file *file,
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unsigned int cmd, unsigned long arg)
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{
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int ret = -ENOTTY;
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int heartbeat_seconds;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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ret = copy_to_user((struct watchdog_info *)arg, &ident,
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sizeof(ident)) ? -EFAULT : 0;
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break;
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case WDIOC_GETSTATUS:
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case WDIOC_GETBOOTSTATUS:
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ret = put_user(0, (int *)arg);
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break;
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case WDIOC_KEEPALIVE:
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jz4740_wdt_service();
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return 0;
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case WDIOC_SETTIMEOUT:
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if (get_user(heartbeat_seconds, (int __user *)arg))
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return -EFAULT;
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jz4740_wdt_set_heartbeat(heartbeat_seconds);
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return 0;
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case WDIOC_GETTIMEOUT:
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return put_user(heartbeat, (int *)arg);
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default:
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break;
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}
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return ret;
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}
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static int jz4740_wdt_release(struct inode *inode, struct file *file)
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{
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jz4740_wdt_service();
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if (test_and_clear_bit(WDT_OK_TO_CLOSE, &jz4740_wdt.status))
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jz4740_wdt_disable();
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clear_bit(WDT_IN_USE, &jz4740_wdt.status);
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return 0;
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}
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static const struct file_operations jz4740_wdt_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = jz4740_wdt_write,
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.unlocked_ioctl = jz4740_wdt_ioctl,
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.open = jz4740_wdt_open,
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.release = jz4740_wdt_release,
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static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
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{
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jz4740_timer_enable_watchdog();
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jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
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return 0;
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}
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static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
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jz4740_timer_disable_watchdog();
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writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
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return 0;
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}
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static const struct watchdog_info jz4740_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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.identity = "jz4740 Watchdog",
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};
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static struct miscdevice jz4740_wdt_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &jz4740_wdt_fops,
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static const struct watchdog_ops jz4740_wdt_ops = {
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.owner = THIS_MODULE,
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.start = jz4740_wdt_start,
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.stop = jz4740_wdt_stop,
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.ping = jz4740_wdt_ping,
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.set_timeout = jz4740_wdt_set_timeout,
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};
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static int __devinit jz4740_wdt_probe(struct platform_device *pdev)
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{
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int ret = 0, size;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct jz4740_wdt_drvdata *drvdata;
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struct watchdog_device *jz4740_wdt;
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struct resource *res;
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int ret;
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drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
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GFP_KERNEL);
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if (!drvdata) {
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dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
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return -ENOMEM;
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}
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if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
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heartbeat = DEFAULT_HEARTBEAT;
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jz4740_wdt = &drvdata->wdt;
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jz4740_wdt->info = &jz4740_wdt_info;
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jz4740_wdt->ops = &jz4740_wdt_ops;
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jz4740_wdt->timeout = heartbeat;
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jz4740_wdt->min_timeout = 1;
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jz4740_wdt->max_timeout = MAX_HEARTBEAT;
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watchdog_set_nowayout(jz4740_wdt, nowayout);
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watchdog_set_drvdata(jz4740_wdt, drvdata);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(dev, "failed to get memory region resource\n");
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return -ENXIO;
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}
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size = resource_size(res);
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jz4740_wdt.mem = request_mem_region(res->start, size, pdev->name);
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if (jz4740_wdt.mem == NULL) {
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dev_err(dev, "failed to get memory region\n");
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return -EBUSY;
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}
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jz4740_wdt.base = ioremap_nocache(res->start, size);
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if (jz4740_wdt.base == NULL) {
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dev_err(dev, "failed to map memory region\n");
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drvdata->base = devm_request_and_ioremap(&pdev->dev, res);
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if (drvdata->base == NULL) {
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ret = -EBUSY;
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goto err_release_region;
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goto err_out;
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}
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jz4740_wdt.rtc_clk = clk_get(NULL, "rtc");
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if (IS_ERR(jz4740_wdt.rtc_clk)) {
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dev_err(dev, "cannot find RTC clock\n");
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ret = PTR_ERR(jz4740_wdt.rtc_clk);
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goto err_iounmap;
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drvdata->rtc_clk = clk_get(NULL, "rtc");
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if (IS_ERR(drvdata->rtc_clk)) {
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dev_err(&pdev->dev, "cannot find RTC clock\n");
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ret = PTR_ERR(drvdata->rtc_clk);
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goto err_out;
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}
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ret = misc_register(&jz4740_wdt_miscdev);
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if (ret < 0) {
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dev_err(dev, "cannot register misc device\n");
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ret = watchdog_register_device(&drvdata->wdt);
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if (ret < 0)
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goto err_disable_clk;
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}
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platform_set_drvdata(pdev, drvdata);
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return 0;
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err_disable_clk:
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clk_put(jz4740_wdt.rtc_clk);
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err_iounmap:
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iounmap(jz4740_wdt.base);
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err_release_region:
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release_mem_region(jz4740_wdt.mem->start,
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resource_size(jz4740_wdt.mem));
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clk_put(drvdata->rtc_clk);
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err_out:
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return ret;
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}
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static int __devexit jz4740_wdt_remove(struct platform_device *pdev)
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{
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jz4740_wdt_disable();
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misc_deregister(&jz4740_wdt_miscdev);
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clk_put(jz4740_wdt.rtc_clk);
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struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
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iounmap(jz4740_wdt.base);
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jz4740_wdt.base = NULL;
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release_mem_region(jz4740_wdt.mem->start,
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resource_size(jz4740_wdt.mem));
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jz4740_wdt.mem = NULL;
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jz4740_wdt_stop(&drvdata->wdt);
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watchdog_unregister_device(&drvdata->wdt);
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clk_put(drvdata->rtc_clk);
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return 0;
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}
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static struct platform_driver jz4740_wdt_driver = {
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.probe = jz4740_wdt_probe,
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.remove = __devexit_p(jz4740_wdt_remove),
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@ -299,13 +220,6 @@ module_platform_driver(jz4740_wdt_driver);
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_DESCRIPTION("jz4740 Watchdog Driver");
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat period in seconds from 1 to "
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__MODULE_STRING(MAX_HEARTBEAT) ", default "
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__MODULE_STRING(DEFAULT_HEARTBEAT));
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MODULE_LICENSE("GPL");
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MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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MODULE_ALIAS("platform:jz4740-wdt");
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