X-gene DTS changes queued for v4.9
This change set includes: + DTS entry to enable SoC PMU for X-Gene v1 SoC + DTS entry to enable SoC PMU for X-Gene v2 SoC + PCIe legacy interrupt polarity fix for X-Gene + X-Gene SoC hwmon DTS entry + DTS entries for X-Gene v2 CPU clock -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX24y0AAoJEB11UG/BVQ/ghjgQAJBb7Hh523y8fRDVHx+/WIvv yMVqQtEGVGE9ATaVbofpQ4InCQzRNWA+lCX35Uw01k9PXixmevPnDvhUzocIeIGD uAKZrQHMMUuM6NyC8doPwWa27ouT0PkB4ZorDlnzjSV5aDC/C8nFXN/0CCnUwzdv nvR3Y3a4207l63FXhSaL0IkE0SXocFOYAvkCtws/rJExJkzrEksTwKQV0j1yxfxb urF+/fH2TgrApOucvQv0POZFLoRq4ZkkEjvWYgYB9VSo++ytpp/hl2uLfASduhqT AvoNiooQk5iir8oFWY0WQNWOsR4qm1IJ44Q1OnjIhi6THzLSCr2NnFBFkEYagW2P ViA332ZwBGOTheuQAfqadqDMn9/ZKm6aM7j6FnvT77fDUSoRZGFh/27/xNSo2jKD 4Oz19AipJuy86NNSfnnfGUewUuPgQrP1p8KovjkkhSOIaU26ftrWNT7v+k7l0ZTH VoHBV835PoEEPyCiRK/++p8zzp8cfQANA0wS1B4ramPyzusZYc16AQmjiUZdcMUZ hIhFrwahU4zP2+jqwLmAosblYGujbgoUVRuViGix4r6HOde+W3gTC5m562DmPFCi MW/L1a53TYslzTI9l2KP+QGL77Eb+87ZDsUEQSZUvK8rGHlo1IetLgP4cppndFq7 C5SEu8DbprXXjPq5A4fp =QQcM -----END PGP SIGNATURE----- Merge tag 'xgene-dts-for-v4.9' of https://github.com/AppliedMicro/xgene-next into next/dt64 Pull "X-gene DTS changes queued for v4.9" from Duc Dang: This change set includes: + DTS entry to enable SoC PMU for X-Gene v1 SoC + DTS entry to enable SoC PMU for X-Gene v2 SoC + PCIe legacy interrupt polarity fix for X-Gene + X-Gene SoC hwmon DTS entry + DTS entries for X-Gene v2 CPU clock * tag 'xgene-dts-for-v4.9' of https://github.com/AppliedMicro/xgene-next: arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks arm64: dts: apm: Add X-Gene SoC hwmon to device tree arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries
This commit is contained in:
Arnd Bergmann
commit
85f8f5938c
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@ -26,6 +26,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_0>;
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#clock-cells = <1>;
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clocks = <&pmd0clk 0>;
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};
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cpu@001 {
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device_type = "cpu";
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@ -34,6 +36,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_0>;
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#clock-cells = <1>;
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clocks = <&pmd0clk 0>;
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};
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cpu@100 {
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device_type = "cpu";
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@ -42,6 +46,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_1>;
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#clock-cells = <1>;
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clocks = <&pmd1clk 0>;
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};
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cpu@101 {
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device_type = "cpu";
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@ -50,6 +56,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_1>;
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#clock-cells = <1>;
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clocks = <&pmd1clk 0>;
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};
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cpu@200 {
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device_type = "cpu";
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@ -58,6 +66,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_2>;
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#clock-cells = <1>;
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clocks = <&pmd2clk 0>;
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};
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cpu@201 {
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device_type = "cpu";
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@ -66,6 +76,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_2>;
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#clock-cells = <1>;
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clocks = <&pmd2clk 0>;
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};
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cpu@300 {
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device_type = "cpu";
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@ -74,6 +86,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_3>;
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#clock-cells = <1>;
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clocks = <&pmd3clk 0>;
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};
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cpu@301 {
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device_type = "cpu";
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@ -82,6 +96,8 @@
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_3>;
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#clock-cells = <1>;
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clocks = <&pmd3clk 0>;
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};
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xgene_L2_0: l2-cache-0 {
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compatible = "cache";
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@ -223,6 +239,46 @@
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clock-output-names = "refclk";
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};
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pmdpll: pmdpll@170000f0 {
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compatible = "apm,xgene-pcppll-v2-clock";
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#clock-cells = <1>;
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clocks = <&refclk 0>;
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reg = <0x0 0x170000f0 0x0 0x10>;
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clock-output-names = "pmdpll";
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};
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pmd0clk: pmd0clk@7e200200 {
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compatible = "apm,xgene-pmd-clock";
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#clock-cells = <1>;
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clocks = <&pmdpll 0>;
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reg = <0x0 0x7e200200 0x0 0x10>;
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clock-output-names = "pmd0clk";
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};
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pmd1clk: pmd1clk@7e200210 {
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compatible = "apm,xgene-pmd-clock";
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#clock-cells = <1>;
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clocks = <&pmdpll 0>;
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reg = <0x0 0x7e200210 0x0 0x10>;
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clock-output-names = "pmd1clk";
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};
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pmd2clk: pmd2clk@7e200220 {
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compatible = "apm,xgene-pmd-clock";
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#clock-cells = <1>;
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clocks = <&pmdpll 0>;
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reg = <0x0 0x7e200220 0x0 0x10>;
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clock-output-names = "pmd2clk";
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};
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pmd3clk: pmd3clk@7e200230 {
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compatible = "apm,xgene-pmd-clock";
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#clock-cells = <1>;
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clocks = <&pmdpll 0>;
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reg = <0x0 0x7e200230 0x0 0x10>;
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clock-output-names = "pmd3clk";
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};
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socpll: socpll@17000120 {
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compatible = "apm,xgene-socpll-v2-clock";
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#clock-cells = <1>;
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@ -453,6 +509,64 @@
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};
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};
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pmu: pmu@78810000 {
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compatible = "apm,xgene-pmu-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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reg = <0x0 0x78810000 0x0 0x1000>;
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interrupts = <0x0 0x22 0x4>;
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pmul3c@7e610000 {
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compatible = "apm,xgene-pmu-l3c";
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reg = <0x0 0x7e610000 0x0 0x1000>;
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};
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pmuiob@7e940000 {
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compatible = "apm,xgene-pmu-iob";
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reg = <0x0 0x7e940000 0x0 0x1000>;
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};
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pmucmcb@7e710000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e710000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmcb@7e730000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e730000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e810000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e810000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmc@7e850000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e850000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e890000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e890000 0x0 0x1000>;
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enable-bit-index = <2>;
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};
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pmucmc@7e8d0000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e8d0000 0x0 0x1000>;
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enable-bit-index = <3>;
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};
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};
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mailbox: mailbox@10540000 {
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compatible = "apm,xgene-slimpro-mbox";
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reg = <0x0 0x10540000 0x0 0x8000>;
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@ -472,6 +586,11 @@
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mboxes = <&mailbox 0>;
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};
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hwmonslimpro {
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compatible = "apm,xgene-slimpro-hwmon";
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mboxes = <&mailbox 7>;
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};
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serial0: serial@10600000 {
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device_type = "serial";
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compatible = "ns16550";
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@ -508,10 +627,10 @@
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
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dma-coherent;
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clocks = <&pcie0clk 0>;
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msi-parent = <&v2m0>;
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@ -533,10 +652,10 @@
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
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dma-coherent;
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clocks = <&pcie1clk 0>;
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msi-parent = <&v2m0>;
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@ -553,6 +553,64 @@
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};
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};
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pmu: pmu@78810000 {
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compatible = "apm,xgene-pmu-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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reg = <0x0 0x78810000 0x0 0x1000>;
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interrupts = <0x0 0x22 0x4>;
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pmul3c@7e610000 {
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compatible = "apm,xgene-pmu-l3c";
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reg = <0x0 0x7e610000 0x0 0x1000>;
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};
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pmuiob@7e940000 {
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compatible = "apm,xgene-pmu-iob";
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reg = <0x0 0x7e940000 0x0 0x1000>;
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};
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pmucmcb@7e710000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e710000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmcb@7e730000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e730000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e810000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e810000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmc@7e850000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e850000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e890000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e890000 0x0 0x1000>;
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enable-bit-index = <2>;
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};
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pmucmc@7e8d0000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e8d0000 0x0 0x1000>;
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enable-bit-index = <3>;
|
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};
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||||
};
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|
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pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
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||||
device_type = "pci";
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||||
|
|
@ -569,10 +627,10 @@
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
msi-parent = <&msi>;
|
||||
|
|
@ -594,10 +652,10 @@
|
|||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie1clk 0>;
|
||||
msi-parent = <&msi>;
|
||||
|
|
@ -619,10 +677,10 @@
|
|||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie2clk 0>;
|
||||
msi-parent = <&msi>;
|
||||
|
|
@ -644,10 +702,10 @@
|
|||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie3clk 0>;
|
||||
msi-parent = <&msi>;
|
||||
|
|
@ -669,10 +727,10 @@
|
|||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie4clk 0>;
|
||||
msi-parent = <&msi>;
|
||||
|
|
@ -697,6 +755,11 @@
|
|||
mboxes = <&mailbox 0>;
|
||||
};
|
||||
|
||||
hwmonslimpro {
|
||||
compatible = "apm,xgene-slimpro-hwmon";
|
||||
mboxes = <&mailbox 7>;
|
||||
};
|
||||
|
||||
serial0: serial@1c020000 {
|
||||
status = "disabled";
|
||||
device_type = "serial";
|
||||
|
|
|
|||
Loading…
Reference in a new issue