CPUidle cleanup
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqDpTAAoJEBvUPslcq6VzKFAQAJXs88lbNxWtJa0cWPt3ugtJ JMX5Lk6VtWL07c7KaWWszgd+IMBBOhJWbzRUNnlXZ+wPLDE31RJErIN51YYM8J3u eTPxoIjeu3Yj1Gba1iT4pHlntOftdu8/B7+7SRxJ22hCHzqUNvFnBGUtXtuUXa+v nT1N7AImqqfO0u16i31G/4NO+H51hz4zuutlBmtZMxW2PaXTqW9WvMrTIMK7yDHn vFX9BhGO7RZJjp3yB8tVD2YpE2Wv1PcMt/iAxetovN28bfWDZCsc6cvtEAnNktOT AGbcdiEU1fSP6CZwxNpybvJjoO16uc6xJ6iDvADcH1e4U6yOPMoJlFQNt4Ay9ljs qYW7kQuOU4BH00/YQXheRAevyO83dtJbrjiryR6LxqUXqyD6K3pxfcCkWM3AU7V3 eqaNLFCyyn6JPxq9gWM9mj/AGwThT2Vq73oZw9NiuocrYMGKOdm14j9SWE+z6ODk 8/F3Gk+z5kF1BoSoho2NcqDiDPwECa0NzdE2WVAMZNiYVHe+CR713DADR4Vlthqc SCw3dDN0z0gegf16Jr8ooKppqcetMQ3rYgQvZtO0PFhmprXdFYU35o79ycW1k5cD QOL2w7hNYGuXeWRgbuMUz9TNklx873+s2MPvtPmXIc8vB2z2bHmD6tKVz5RZBtuu e4Je7Qmb34qbiUHK/oDG =B9ka -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-cpuidle-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup CPUidle cleanup By Daniel Lezcano via Kevin Hilman (1) and Tony Lindgren (1) * tag 'omap-cleanup-cpuidle-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP3: cpuidle - check the powerdomain lookup ARM: OMAP3: cpuidle - set global variables static ARM: OMAP3: set omap3_idle_data as static ARM: OMAP3: cpuidle - simplify next_valid_state ARM: OMAP3: cpuidle - use omap3_idle_data directly ARM: OMAP3: define statically the omap3_idle_data ARM: OMAP3: cpuidle - remove cpuidle_params_table ARM: OMAP3: cpuidle - remove the 'valid' field ARM: OMAP3: cpuidle - remove errata check in the init function ARM: OMAP3: define cpuidle statically ARM: OMAP3: cpuidle - remove rx51 cpuidle parameters table ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot time ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table ARM: OMAP4: cpuidle - Declare the states with the driver declaration ARM: OMAP4: cpuidle - Remove unused valid field Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
86558257aa
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@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
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};
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/*
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* cpuidle C-states definition override from the default values.
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* The 'exit_latency' field is the sum of sleep and wake-up latencies.
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*/
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static struct cpuidle_params rx51_cpuidle_params[] = {
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/* C1 */
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{110 + 162, 5 , 1},
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/* C2 */
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{106 + 180, 309, 1},
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/* C3 */
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{107 + 410, 46057, 0},
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/* C4 */
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{121 + 3374, 46057, 0},
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/* C5 */
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{855 + 1146, 46057, 1},
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/* C6 */
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{7580 + 4134, 484329, 0},
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/* C7 */
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{7505 + 15274, 484329, 1},
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};
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* cpuidle C-states definition for rx51.
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*
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* The 'exit_latency' field is the sum of sleep
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* and wake-up latencies.
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---------------------------------------------
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| state | exit_latency | target_residency |
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---------------------------------------------
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| C1 | 110 + 162 | 5 |
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| C2 | 106 + 180 | 309 |
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| C3 | 107 + 410 | 46057 |
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| C4 | 121 + 3374 | 46057 |
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| C5 | 855 + 1146 | 46057 |
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| C6 | 7580 + 4134 | 484329 |
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| C7 | 7505 + 15274 | 484329 |
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---------------------------------------------
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*/
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extern void __init rx51_peripherals_init(void);
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@ -98,7 +97,6 @@ static void __init rx51_init(void)
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struct omap_sdrc_params *sdrc_params;
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omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
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omap3_pm_init_cpuidle(rx51_cpuidle_params);
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omap_serial_init();
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sdrc_params = nokia_get_sdram_timings();
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@ -38,40 +38,44 @@
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#ifdef CONFIG_CPU_IDLE
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/*
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* The latencies/thresholds for various C states have
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* to be configured from the respective board files.
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* These are some default values (which might not provide
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* the best power savings) used on boards which do not
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* pass these details from the board file.
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*/
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static struct cpuidle_params cpuidle_params_table[] = {
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/* C1 */
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{2 + 2, 5, 1},
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/* C2 */
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{10 + 10, 30, 1},
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/* C3 */
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{50 + 50, 300, 1},
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/* C4 */
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{1500 + 1800, 4000, 1},
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/* C5 */
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{2500 + 7500, 12000, 1},
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/* C6 */
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{3000 + 8500, 15000, 1},
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/* C7 */
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{10000 + 30000, 300000, 1},
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};
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#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
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/* Mach specific information to be recorded in the C-state driver_data */
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struct omap3_idle_statedata {
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u32 mpu_state;
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u32 core_state;
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u8 valid;
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};
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struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
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struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
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static struct omap3_idle_statedata omap3_idle_data[] = {
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_ON,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_OFF,
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},
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};
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static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
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static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
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struct clockdomain *clkdm)
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@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct omap3_idle_statedata *cx =
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cpuidle_get_statedata(&dev->states_usage[index]);
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
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local_fiq_disable();
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@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev,
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* if it satisfies the enable_off_mode condition.
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*/
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static int next_valid_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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struct cpuidle_driver *drv, int index)
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{
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struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
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struct cpuidle_state *curr = &drv->states[index];
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struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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u32 mpu_deepest_state = PWRDM_POWER_RET;
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u32 core_deepest_state = PWRDM_POWER_RET;
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int idx;
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int next_index = -1;
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if (enable_off_mode) {
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@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev,
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}
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/* Check if current state is valid */
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if ((cx->valid) &&
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(cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state)) {
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state))
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return index;
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} else {
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int idx = OMAP3_NUM_STATES - 1;
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/* Reach the current state starting at highest C-state */
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for (; idx >= 0; idx--) {
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if (&drv->states[idx] == curr) {
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next_index = idx;
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break;
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}
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/*
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* Drop to next valid state.
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* Start search from the next (lower) state.
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*/
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for (idx = index - 1; idx >= 0; idx--) {
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cx = &omap3_idle_data[idx];
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state)) {
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next_index = idx;
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break;
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}
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/* Should never hit this condition */
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WARN_ON(next_index == -1);
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/*
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* Drop to next valid state.
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* Start search from the next (lower) state.
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*/
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idx--;
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for (; idx >= 0; idx--) {
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cx = cpuidle_get_statedata(&dev->states_usage[idx]);
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if ((cx->valid) &&
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(cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state)) {
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next_index = idx;
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break;
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}
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}
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/*
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* C1 is always valid.
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* So, no need to check for 'next_index == -1' outside
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* this loop.
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*/
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}
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/*
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* C1 is always valid.
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* So, no need to check for 'next_index == -1' outside
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* this loop.
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*/
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return next_index;
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}
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@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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* Prevent PER off if CORE is not in retention or off as this
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* would disable PER wakeups completely.
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*/
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cx = cpuidle_get_statedata(&dev->states_usage[index]);
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cx = &omap3_idle_data[index];
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core_next_state = cx->core_state;
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per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
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if ((per_next_state == PWRDM_POWER_OFF) &&
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@ -298,57 +283,71 @@ select_state:
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DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
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void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
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{
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int i;
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if (!cpuidle_board_params)
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return;
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for (i = 0; i < OMAP3_NUM_STATES; i++) {
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cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
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cpuidle_params_table[i].exit_latency =
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cpuidle_board_params[i].exit_latency;
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cpuidle_params_table[i].target_residency =
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cpuidle_board_params[i].target_residency;
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}
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return;
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}
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struct cpuidle_driver omap3_idle_driver = {
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.name = "omap3_idle",
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.owner = THIS_MODULE,
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.states = {
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{
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.enter = omap3_enter_idle,
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10 + 10,
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.target_residency = 30,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C2",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 50 + 50,
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.target_residency = 300,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C3",
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.desc = "MPU RET + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 1500 + 1800,
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.target_residency = 4000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C4",
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.desc = "MPU OFF + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2500 + 7500,
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.target_residency = 12000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C5",
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.desc = "MPU RET + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 3000 + 8500,
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.target_residency = 15000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C6",
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.desc = "MPU OFF + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10000 + 30000,
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.target_residency = 30000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C7",
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.desc = "MPU OFF + CORE OFF",
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},
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},
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.state_count = ARRAY_SIZE(omap3_idle_data),
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.safe_state_index = 0,
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};
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/* Helper to fill the C-state common data*/
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static inline void _fill_cstate(struct cpuidle_driver *drv,
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int idx, const char *descr)
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{
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struct cpuidle_state *state = &drv->states[idx];
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state->exit_latency = cpuidle_params_table[idx].exit_latency;
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state->target_residency = cpuidle_params_table[idx].target_residency;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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state->enter = omap3_enter_idle_bm;
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sprintf(state->name, "C%d", idx + 1);
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strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
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}
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/* Helper to register the driver_data */
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static inline struct omap3_idle_statedata *_fill_cstate_usage(
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struct cpuidle_device *dev,
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int idx)
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{
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struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
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struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
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cx->valid = cpuidle_params_table[idx].valid;
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cpuidle_set_statedata(state_usage, cx);
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return cx;
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}
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/**
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* omap3_idle_init - Init routine for OMAP3 idle
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*
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@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
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int __init omap3_idle_init(void)
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{
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struct cpuidle_device *dev;
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struct cpuidle_driver *drv = &omap3_idle_driver;
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struct omap3_idle_statedata *cx;
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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core_pd = pwrdm_lookup("core_pwrdm");
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per_pd = pwrdm_lookup("per_pwrdm");
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cam_pd = pwrdm_lookup("cam_pwrdm");
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if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
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return -ENODEV;
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drv->safe_state_index = -1;
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dev = &per_cpu(omap3_idle_dev, smp_processor_id());
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/* C1 . MPU WFI + Core active */
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_fill_cstate(drv, 0, "MPU ON + CORE ON");
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(&drv->states[0])->enter = omap3_enter_idle;
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drv->safe_state_index = 0;
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cx = _fill_cstate_usage(dev, 0);
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cx->valid = 1; /* C1 is always valid */
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cx->mpu_state = PWRDM_POWER_ON;
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cx->core_state = PWRDM_POWER_ON;
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/* C2 . MPU WFI + Core inactive */
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_fill_cstate(drv, 1, "MPU ON + CORE ON");
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cx = _fill_cstate_usage(dev, 1);
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cx->mpu_state = PWRDM_POWER_ON;
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cx->core_state = PWRDM_POWER_ON;
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/* C3 . MPU CSWR + Core inactive */
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_fill_cstate(drv, 2, "MPU RET + CORE ON");
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cx = _fill_cstate_usage(dev, 2);
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cx->mpu_state = PWRDM_POWER_RET;
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cx->core_state = PWRDM_POWER_ON;
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/* C4 . MPU OFF + Core inactive */
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_fill_cstate(drv, 3, "MPU OFF + CORE ON");
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cx = _fill_cstate_usage(dev, 3);
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cx->mpu_state = PWRDM_POWER_OFF;
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cx->core_state = PWRDM_POWER_ON;
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/* C5 . MPU RET + Core RET */
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_fill_cstate(drv, 4, "MPU RET + CORE RET");
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cx = _fill_cstate_usage(dev, 4);
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cx->mpu_state = PWRDM_POWER_RET;
|
||||
cx->core_state = PWRDM_POWER_RET;
|
||||
|
||||
/* C6 . MPU OFF + Core RET */
|
||||
_fill_cstate(drv, 5, "MPU OFF + CORE RET");
|
||||
cx = _fill_cstate_usage(dev, 5);
|
||||
cx->mpu_state = PWRDM_POWER_OFF;
|
||||
cx->core_state = PWRDM_POWER_RET;
|
||||
|
||||
/* C7 . MPU OFF + Core OFF */
|
||||
_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
|
||||
cx = _fill_cstate_usage(dev, 6);
|
||||
/*
|
||||
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
|
||||
* enable OFF mode in a stable form for previous revisions.
|
||||
* We disable C7 state as a result.
|
||||
*/
|
||||
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
|
||||
cx->valid = 0;
|
||||
pr_warn("%s: core off state C7 disabled due to i583\n",
|
||||
__func__);
|
||||
}
|
||||
cx->mpu_state = PWRDM_POWER_OFF;
|
||||
cx->core_state = PWRDM_POWER_OFF;
|
||||
|
||||
drv->state_count = OMAP3_NUM_STATES;
|
||||
cpuidle_register_driver(&omap3_idle_driver);
|
||||
|
||||
dev->state_count = OMAP3_NUM_STATES;
|
||||
dev = &per_cpu(omap3_idle_dev, smp_processor_id());
|
||||
dev->cpu = 0;
|
||||
|
||||
if (cpuidle_register_device(dev)) {
|
||||
printk(KERN_ERR "%s: CPUidle register device failed\n",
|
||||
__func__);
|
||||
|
|
|
@ -24,26 +24,31 @@
|
|||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
|
||||
/* Machine specific information to be recorded in the C-state driver_data */
|
||||
/* Machine specific information */
|
||||
struct omap4_idle_statedata {
|
||||
u32 cpu_state;
|
||||
u32 mpu_logic_state;
|
||||
u32 mpu_state;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
static struct cpuidle_params cpuidle_params_table[] = {
|
||||
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
|
||||
{.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
|
||||
/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
|
||||
{.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
|
||||
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
|
||||
{.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
|
||||
static struct omap4_idle_statedata omap4_idle_data[] = {
|
||||
{
|
||||
.cpu_state = PWRDM_POWER_ON,
|
||||
.mpu_state = PWRDM_POWER_ON,
|
||||
.mpu_logic_state = PWRDM_POWER_RET,
|
||||
},
|
||||
{
|
||||
.cpu_state = PWRDM_POWER_OFF,
|
||||
.mpu_state = PWRDM_POWER_RET,
|
||||
.mpu_logic_state = PWRDM_POWER_RET,
|
||||
},
|
||||
{
|
||||
.cpu_state = PWRDM_POWER_OFF,
|
||||
.mpu_state = PWRDM_POWER_RET,
|
||||
.mpu_logic_state = PWRDM_POWER_OFF,
|
||||
},
|
||||
};
|
||||
|
||||
#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
|
||||
|
||||
struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
|
||||
static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
|
||||
|
||||
/**
|
||||
|
@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
struct omap4_idle_statedata *cx =
|
||||
cpuidle_get_statedata(&dev->states_usage[index]);
|
||||
struct omap4_idle_statedata *cx = &omap4_idle_data[index];
|
||||
u32 cpu1_state;
|
||||
int cpu_id = smp_processor_id();
|
||||
|
||||
|
@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
|
|||
cpu1_state = pwrdm_read_pwrst(cpu1_pd);
|
||||
if (cpu1_state != PWRDM_POWER_OFF) {
|
||||
index = drv->safe_state_index;
|
||||
cx = cpuidle_get_statedata(&dev->states_usage[index]);
|
||||
cx = &omap4_idle_data[index];
|
||||
}
|
||||
|
||||
if (index > 0)
|
||||
|
@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = {
|
|||
.name = "omap4_idle",
|
||||
.owner = THIS_MODULE,
|
||||
.en_core_tk_irqen = 1,
|
||||
.states = {
|
||||
{
|
||||
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
|
||||
.exit_latency = 2 + 2,
|
||||
.target_residency = 5,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.enter = omap4_enter_idle,
|
||||
.name = "C1",
|
||||
.desc = "MPUSS ON"
|
||||
},
|
||||
{
|
||||
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
|
||||
.exit_latency = 328 + 440,
|
||||
.target_residency = 960,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.enter = omap4_enter_idle,
|
||||
.name = "C2",
|
||||
.desc = "MPUSS CSWR",
|
||||
},
|
||||
{
|
||||
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
|
||||
.exit_latency = 460 + 518,
|
||||
.target_residency = 1100,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.enter = omap4_enter_idle,
|
||||
.name = "C3",
|
||||
.desc = "MPUSS OSWR",
|
||||
},
|
||||
},
|
||||
.state_count = ARRAY_SIZE(omap4_idle_data),
|
||||
.safe_state_index = 0,
|
||||
};
|
||||
|
||||
static inline void _fill_cstate(struct cpuidle_driver *drv,
|
||||
int idx, const char *descr)
|
||||
{
|
||||
struct cpuidle_state *state = &drv->states[idx];
|
||||
|
||||
state->exit_latency = cpuidle_params_table[idx].exit_latency;
|
||||
state->target_residency = cpuidle_params_table[idx].target_residency;
|
||||
state->flags = CPUIDLE_FLAG_TIME_VALID;
|
||||
state->enter = omap4_enter_idle;
|
||||
sprintf(state->name, "C%d", idx + 1);
|
||||
strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
|
||||
}
|
||||
|
||||
static inline struct omap4_idle_statedata *_fill_cstate_usage(
|
||||
struct cpuidle_device *dev,
|
||||
int idx)
|
||||
{
|
||||
struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
|
||||
struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
|
||||
|
||||
cx->valid = cpuidle_params_table[idx].valid;
|
||||
cpuidle_set_statedata(state_usage, cx);
|
||||
|
||||
return cx;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* omap4_idle_init - Init routine for OMAP4 idle
|
||||
*
|
||||
|
@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
|
|||
*/
|
||||
int __init omap4_idle_init(void)
|
||||
{
|
||||
struct omap4_idle_statedata *cx;
|
||||
struct cpuidle_device *dev;
|
||||
struct cpuidle_driver *drv = &omap4_idle_driver;
|
||||
unsigned int cpu_id = 0;
|
||||
|
||||
mpu_pd = pwrdm_lookup("mpu_pwrdm");
|
||||
|
@ -182,42 +187,15 @@ int __init omap4_idle_init(void)
|
|||
if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
drv->safe_state_index = -1;
|
||||
dev = &per_cpu(omap4_idle_dev, cpu_id);
|
||||
dev->cpu = cpu_id;
|
||||
|
||||
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
|
||||
_fill_cstate(drv, 0, "MPUSS ON");
|
||||
drv->safe_state_index = 0;
|
||||
cx = _fill_cstate_usage(dev, 0);
|
||||
cx->valid = 1; /* C1 is always valid */
|
||||
cx->cpu_state = PWRDM_POWER_ON;
|
||||
cx->mpu_state = PWRDM_POWER_ON;
|
||||
cx->mpu_logic_state = PWRDM_POWER_RET;
|
||||
|
||||
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
|
||||
_fill_cstate(drv, 1, "MPUSS CSWR");
|
||||
cx = _fill_cstate_usage(dev, 1);
|
||||
cx->cpu_state = PWRDM_POWER_OFF;
|
||||
cx->mpu_state = PWRDM_POWER_RET;
|
||||
cx->mpu_logic_state = PWRDM_POWER_RET;
|
||||
|
||||
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
|
||||
_fill_cstate(drv, 2, "MPUSS OSWR");
|
||||
cx = _fill_cstate_usage(dev, 2);
|
||||
cx->cpu_state = PWRDM_POWER_OFF;
|
||||
cx->mpu_state = PWRDM_POWER_RET;
|
||||
cx->mpu_logic_state = PWRDM_POWER_OFF;
|
||||
|
||||
drv->state_count = OMAP4_NUM_STATES;
|
||||
cpuidle_register_driver(&omap4_idle_driver);
|
||||
|
||||
dev->state_count = OMAP4_NUM_STATES;
|
||||
if (cpuidle_register_device(dev)) {
|
||||
pr_err("%s: CPUidle register device failed\n", __func__);
|
||||
return -EIO;
|
||||
}
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -38,27 +38,6 @@ static inline int omap4_opp_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cpuidle mach specific parameters
|
||||
*
|
||||
* The board code can override the default C-states definition using
|
||||
* omap3_pm_init_cpuidle
|
||||
*/
|
||||
struct cpuidle_params {
|
||||
u32 exit_latency; /* exit_latency = sleep + wake-up latencies */
|
||||
u32 target_residency;
|
||||
u8 valid; /* validates the C-state */
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
|
||||
extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
|
||||
#else
|
||||
static
|
||||
inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
|
||||
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
|
||||
|
||||
|
|
Loading…
Reference in a new issue