drm/radeon/cik: restructure rlc setup
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7235711a43
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866d83de0c
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@ -60,6 +60,7 @@ extern bool evergreen_is_display_hung(struct radeon_device *rdev);
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extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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extern void si_rlc_fini(struct radeon_device *rdev);
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extern void si_rlc_fini(struct radeon_device *rdev);
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extern int si_rlc_init(struct radeon_device *rdev);
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extern int si_rlc_init(struct radeon_device *rdev);
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extern void si_rlc_reset(struct radeon_device *rdev);
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static void cik_rlc_stop(struct radeon_device *rdev);
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static void cik_rlc_stop(struct radeon_device *rdev);
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static void cik_pcie_gen3_enable(struct radeon_device *rdev);
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static void cik_pcie_gen3_enable(struct radeon_device *rdev);
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static void cik_program_aspm(struct radeon_device *rdev);
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static void cik_program_aspm(struct radeon_device *rdev);
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@ -4728,31 +4729,34 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm
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* variety of functions, the most important of which is
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* variety of functions, the most important of which is
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* the interrupt controller.
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* the interrupt controller.
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*/
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*/
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/**
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static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
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* cik_rlc_stop - stop the RLC ME
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bool enable)
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*
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* @rdev: radeon_device pointer
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*
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* Halt the RLC ME (MicroEngine) (CIK).
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*/
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static void cik_rlc_stop(struct radeon_device *rdev)
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{
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{
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int i, j, k;
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u32 tmp = RREG32(CP_INT_CNTL_RING0);
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u32 mask, tmp;
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tmp = RREG32(CP_INT_CNTL_RING0);
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if (enable)
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tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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else
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tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING0, tmp);
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WREG32(CP_INT_CNTL_RING0, tmp);
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}
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RREG32(CB_CGTT_SCLK_CTRL);
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static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
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RREG32(CB_CGTT_SCLK_CTRL);
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{
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RREG32(CB_CGTT_SCLK_CTRL);
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u32 tmp;
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RREG32(CB_CGTT_SCLK_CTRL);
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tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
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tmp = RREG32(RLC_LB_CNTL);
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WREG32(RLC_CGCG_CGLS_CTRL, tmp);
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if (enable)
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tmp |= LOAD_BALANCE_ENABLE;
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else
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tmp &= ~LOAD_BALANCE_ENABLE;
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WREG32(RLC_LB_CNTL, tmp);
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}
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WREG32(RLC_CNTL, 0);
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static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
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{
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u32 i, j, k;
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u32 mask;
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for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
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for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
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for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
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for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
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@ -4774,6 +4778,32 @@ static void cik_rlc_stop(struct radeon_device *rdev)
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}
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}
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}
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}
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/**
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* cik_rlc_stop - stop the RLC ME
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*
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* @rdev: radeon_device pointer
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*
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* Halt the RLC ME (MicroEngine) (CIK).
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*/
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static void cik_rlc_stop(struct radeon_device *rdev)
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{
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u32 tmp;
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cik_enable_gui_idle_interrupt(rdev, false);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
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WREG32(RLC_CGCG_CGLS_CTRL, tmp);
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WREG32(RLC_CNTL, 0);
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cik_wait_for_rlc_serdes(rdev);
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}
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/**
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/**
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* cik_rlc_start - start the RLC ME
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* cik_rlc_start - start the RLC ME
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*
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*
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@ -4783,13 +4813,9 @@ static void cik_rlc_stop(struct radeon_device *rdev)
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*/
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*/
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static void cik_rlc_start(struct radeon_device *rdev)
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static void cik_rlc_start(struct radeon_device *rdev)
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{
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{
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u32 tmp;
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WREG32(RLC_CNTL, RLC_ENABLE);
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WREG32(RLC_CNTL, RLC_ENABLE);
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tmp = RREG32(CP_INT_CNTL_RING0);
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cik_enable_gui_idle_interrupt(rdev, true);
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tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING0, tmp);
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udelay(50);
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udelay(50);
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}
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}
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@ -4827,12 +4853,7 @@ static int cik_rlc_resume(struct radeon_device *rdev)
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cik_rlc_stop(rdev);
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cik_rlc_stop(rdev);
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WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC);
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si_rlc_reset(rdev);
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RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(RLC_LB_CNTR_INIT, 0);
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WREG32(RLC_LB_CNTR_INIT, 0);
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WREG32(RLC_LB_CNTR_MAX, 0x00008000);
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WREG32(RLC_LB_CNTR_MAX, 0x00008000);
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@ -4851,6 +4872,9 @@ static int cik_rlc_resume(struct radeon_device *rdev)
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WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(RLC_GPM_UCODE_ADDR, 0);
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WREG32(RLC_GPM_UCODE_ADDR, 0);
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/* XXX - find out what chips support lbpw */
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cik_enable_lbpw(rdev, false);
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/* XXX */
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/* XXX */
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clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
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clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
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clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
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clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
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@ -905,6 +905,7 @@
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#define RLC_LB_CNTR_MAX 0xC348
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#define RLC_LB_CNTR_MAX 0xC348
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#define RLC_LB_CNTL 0xC364
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#define RLC_LB_CNTL 0xC364
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# define LOAD_BALANCE_ENABLE (1 << 0)
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#define RLC_LB_CNTR_INIT 0xC36C
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#define RLC_LB_CNTR_INIT 0xC36C
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@ -5435,7 +5435,7 @@ int si_rlc_init(struct radeon_device *rdev)
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return 0;
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return 0;
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}
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}
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static void si_rlc_reset(struct radeon_device *rdev)
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void si_rlc_reset(struct radeon_device *rdev)
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{
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{
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u32 tmp = RREG32(GRBM_SOFT_RESET);
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u32 tmp = RREG32(GRBM_SOFT_RESET);
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