drm/radeon/kms: fix up DP clock programming on DCE4/5
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1443,11 +1443,19 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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uint32_t pll_in_use = 0;
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uint32_t pll_in_use = 0;
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE4(rdev)) {
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/* if crtc is driving DP and we have an ext clock, use that */
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list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
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list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
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if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
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if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
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/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
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* depending on the asic:
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* DCE4: PPLL or ext clock
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* DCE5: DCPLL or ext clock
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*
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* Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
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* PPLL/DCPLL programming and only program the DP DTO for the
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* crtc virtual pixel clock.
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*/
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if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
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if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
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if (rdev->clock.dp_extclk)
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if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
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return ATOM_PPLL_INVALID;
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return ATOM_PPLL_INVALID;
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}
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}
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}
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}
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@ -988,11 +988,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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}
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}
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if (ASIC_IS_DCE5(rdev)) {
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if (ASIC_IS_DCE5(rdev)) {
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if (is_dp && rdev->clock.dp_extclk)
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/* On DCE5 DCPLL usually generates the DP ref clock */
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args.v4.acConfig.ucRefClkSource = 3; /* external src */
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if (is_dp) {
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else
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if (rdev->clock.dp_extclk)
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args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
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else
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args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
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} else
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args.v4.acConfig.ucRefClkSource = pll_id;
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args.v4.acConfig.ucRefClkSource = pll_id;
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} else {
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} else {
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/* On DCE4, if there is an external clock, it generates the DP ref clock */
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if (is_dp && rdev->clock.dp_extclk)
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if (is_dp && rdev->clock.dp_extclk)
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args.v3.acConfig.ucRefClkSource = 2; /* external src */
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args.v3.acConfig.ucRefClkSource = 2; /* external src */
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else
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else
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