bnx2x: Parity errors recovery for 578xx
Fix the parity errors recovery flow for 578xx:
- Add a separate column for the 578xx in the parity mask
registers DB.
- Fix the bnx2x_process_kill_chip_reset() to handle the blocks
newly introduced in the 578xx.
Cover ATC and PGLUE_B blocks for 57712 and 578xx.
Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Vladislav Zolotarov
David S. Miller
parent
c03bd39c56
commit
8736c82650
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@ -1920,6 +1920,9 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
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AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
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#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
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AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
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#define RSS_FLAGS(bp) \
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(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
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TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
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@ -326,25 +326,25 @@ struct src_ent {
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/****************************************************************************
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* Parity configuration
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****************************************************************************/
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#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
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#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK, \
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block##_REG_##block##_PRTY_STS_CLR, \
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en_mask, {m1, m1h, m2}, #block \
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en_mask, {m1, m1h, m2, m3}, #block \
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}
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#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
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#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK_0, \
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block##_REG_##block##_PRTY_STS_CLR_0, \
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en_mask, {m1, m1h, m2}, #block"_0" \
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en_mask, {m1, m1h, m2, m3}, #block"_0" \
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}
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#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
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#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
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{ \
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block##_REG_##block##_PRTY_MASK_1, \
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block##_REG_##block##_PRTY_STS_CLR_1, \
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en_mask, {m1, m1h, m2}, #block"_1" \
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en_mask, {m1, m1h, m2, m3}, #block"_1" \
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}
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static const struct {
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@ -355,6 +355,7 @@ static const struct {
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u32 e1; /* 57710 */
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u32 e1h; /* 57711 */
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u32 e2; /* 57712 */
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u32 e3; /* 578xx */
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} reg_mask; /* Register mask (all valid bits) */
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char name[7]; /* Block's longest name is 6 characters long
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* (name + suffix)
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@ -372,48 +373,56 @@ static const struct {
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/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
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* want to handle "system kill" flow at the moment.
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*/
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BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
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BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
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BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0),
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BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff),
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BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xffff),
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BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
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BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
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BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
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BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
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0x7ffffff),
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BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
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BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
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BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
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BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
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BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
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BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
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BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
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{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
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{0xf, 0xf, 0xf}, "UPB"},
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{0xf, 0xf, 0xf, 0xf}, "UPB"},
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{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
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GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
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{0xf, 0xf, 0xf}, "XPB"},
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BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
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BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
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BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffffff),
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BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f),
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BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff),
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BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
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BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
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BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
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{0xf, 0xf, 0xf, 0xf}, "XPB"},
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BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
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BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
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BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
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BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
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BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
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BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
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BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
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BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
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BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
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BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
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BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
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BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
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BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff),
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BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
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};
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@ -464,8 +473,10 @@ static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
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return bnx2x_blocks_parity_data[idx].reg_mask.e1;
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else if (CHIP_IS_E1H(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
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else
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else if (CHIP_IS_E2(bp))
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return bnx2x_blocks_parity_data[idx].reg_mask.e2;
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else /* CHIP_IS_E3 */
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return bnx2x_blocks_parity_data[idx].reg_mask.e3;
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}
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static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
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@ -3817,6 +3817,10 @@ static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
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if (print)
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_print_next_block(par_num++, "USDM");
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break;
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case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
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if (print)
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_print_next_block(par_num++, "UCM");
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break;
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case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
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if (print)
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_print_next_block(par_num++, "USEMI");
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@ -3829,6 +3833,10 @@ static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
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if (print)
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_print_next_block(par_num++, "CSDM");
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break;
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case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
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if (print)
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_print_next_block(par_num++, "CCM");
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break;
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}
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/* Clear the bit */
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@ -3933,32 +3941,67 @@ static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
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return par_num;
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}
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static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
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u32 sig0, u32 sig1, u32 sig2, u32 sig3)
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static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
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bool print)
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{
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if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
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(sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
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int i = 0;
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u32 cur_bit = 0;
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for (i = 0; sig; i++) {
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cur_bit = ((u32)0x1 << i);
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if (sig & cur_bit) {
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switch (cur_bit) {
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case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
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if (print)
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_print_next_block(par_num++, "PGLUE_B");
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break;
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case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
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if (print)
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_print_next_block(par_num++, "ATC");
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break;
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}
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/* Clear the bit */
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sig &= ~cur_bit;
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}
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}
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return par_num;
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}
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static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
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u32 *sig)
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{
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if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
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(sig[1] & HW_PRTY_ASSERT_SET_1) ||
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(sig[2] & HW_PRTY_ASSERT_SET_2) ||
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(sig[3] & HW_PRTY_ASSERT_SET_3) ||
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(sig[4] & HW_PRTY_ASSERT_SET_4)) {
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int par_num = 0;
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DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
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"[0]:0x%08x [1]:0x%08x "
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"[2]:0x%08x [3]:0x%08x\n",
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sig0 & HW_PRTY_ASSERT_SET_0,
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sig1 & HW_PRTY_ASSERT_SET_1,
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sig2 & HW_PRTY_ASSERT_SET_2,
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sig3 & HW_PRTY_ASSERT_SET_3);
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"[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
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"[4]:0x%08x\n",
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sig[0] & HW_PRTY_ASSERT_SET_0,
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sig[1] & HW_PRTY_ASSERT_SET_1,
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sig[2] & HW_PRTY_ASSERT_SET_2,
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sig[3] & HW_PRTY_ASSERT_SET_3,
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sig[4] & HW_PRTY_ASSERT_SET_4);
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if (print)
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netdev_err(bp->dev,
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"Parity errors detected in blocks: ");
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par_num = bnx2x_check_blocks_with_parity0(
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sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
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sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
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par_num = bnx2x_check_blocks_with_parity1(
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sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
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sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
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par_num = bnx2x_check_blocks_with_parity2(
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sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
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sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
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par_num = bnx2x_check_blocks_with_parity3(
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sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
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sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
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par_num = bnx2x_check_blocks_with_parity4(
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sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
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if (print)
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pr_cont("\n");
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return true;
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} else
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return false;
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@ -3973,7 +4016,7 @@ static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
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*/
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bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
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{
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struct attn_route attn;
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struct attn_route attn = { {0} };
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int port = BP_PORT(bp);
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attn.sig[0] = REG_RD(bp,
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@ -3989,8 +4032,12 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
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MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
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port*4);
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return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
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attn.sig[2], attn.sig[3]);
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if (!CHIP_IS_E1x(bp))
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attn.sig[4] = REG_RD(bp,
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MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
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port*4);
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return bnx2x_parity_attn(bp, global, print, attn.sig);
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}
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@ -7932,7 +7979,7 @@ static void bnx2x_pxp_prep(struct bnx2x *bp)
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static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
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{
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u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
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u32 global_bits2;
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u32 global_bits2, stay_reset2;
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/*
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* Bits that have to be set in reset_mask2 if we want to reset 'global'
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@ -7942,6 +7989,7 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
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MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
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MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
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/* Don't reset the following blocks */
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not_reset_mask1 =
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MISC_REGISTERS_RESET_REG_1_RST_HC |
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MISC_REGISTERS_RESET_REG_1_RST_PXPV |
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@ -7955,19 +8003,35 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
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MISC_REGISTERS_RESET_REG_2_RST_RBCN |
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MISC_REGISTERS_RESET_REG_2_RST_GRC |
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MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
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MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
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||||
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
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||||
MISC_REGISTERS_RESET_REG_2_RST_ATC |
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||||
MISC_REGISTERS_RESET_REG_2_PGLC;
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||||
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||||
/*
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||||
* Keep the following blocks in reset:
|
||||
* - all xxMACs are handled by the bnx2x_link code.
|
||||
*/
|
||||
stay_reset2 =
|
||||
MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
|
||||
MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
|
||||
MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
|
||||
MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
|
||||
MISC_REGISTERS_RESET_REG_2_UMAC0 |
|
||||
MISC_REGISTERS_RESET_REG_2_UMAC1 |
|
||||
MISC_REGISTERS_RESET_REG_2_XMAC |
|
||||
MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
|
||||
|
||||
/* Full reset masks according to the chip */
|
||||
reset_mask1 = 0xffffffff;
|
||||
|
||||
if (CHIP_IS_E1(bp))
|
||||
reset_mask2 = 0xffff;
|
||||
else
|
||||
else if (CHIP_IS_E1H(bp))
|
||||
reset_mask2 = 0x1ffff;
|
||||
|
||||
if (CHIP_IS_E3(bp)) {
|
||||
reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
|
||||
reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
|
||||
}
|
||||
else if (CHIP_IS_E2(bp))
|
||||
reset_mask2 = 0xfffff;
|
||||
else /* CHIP_IS_E3 */
|
||||
reset_mask2 = 0x3ffffff;
|
||||
|
||||
/* Don't reset global blocks unless we need to */
|
||||
if (!global)
|
||||
|
|
@ -7996,7 +8060,12 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
|
|||
barrier();
|
||||
mmiowb();
|
||||
|
||||
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
|
||||
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
|
||||
reset_mask2 & (~stay_reset2));
|
||||
|
||||
barrier();
|
||||
mmiowb();
|
||||
|
||||
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
|
||||
mmiowb();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,7 +32,11 @@
|
|||
/* [R 1] ATC initalization done */
|
||||
#define ATC_REG_ATC_INIT_DONE 0x1100bc
|
||||
/* [RC 6] Interrupt register #0 read clear */
|
||||
#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
|
||||
#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
|
||||
/* [RW 5] Parity mask register #0 read/write */
|
||||
#define ATC_REG_ATC_PRTY_MASK 0x1101d8
|
||||
/* [RC 5] Parity register #0 read clear */
|
||||
#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
|
||||
/* [RW 19] Interrupt mask register #0 read/write */
|
||||
#define BRB1_REG_BRB1_INT_MASK 0x60128
|
||||
/* [R 19] Interrupt register #0 read */
|
||||
|
|
@ -2676,8 +2680,12 @@
|
|||
#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
|
||||
/* [RC 9] Interrupt register #0 read clear */
|
||||
#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
|
||||
/* [RW 2] Parity mask register #0 read/write */
|
||||
#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
|
||||
/* [R 2] Parity register #0 read */
|
||||
#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
|
||||
/* [RC 2] Parity register #0 read clear */
|
||||
#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
|
||||
/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
|
||||
* VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
|
||||
* Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
|
||||
|
|
@ -5686,8 +5694,13 @@
|
|||
#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
|
||||
#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
|
||||
#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
|
||||
#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
|
||||
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
|
||||
|
|
@ -5700,6 +5713,7 @@
|
|||
#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
|
||||
#define MISC_REGISTERS_RESET_REG_2_SET 0x594
|
||||
#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
|
||||
#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
|
||||
#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
|
||||
#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
|
||||
#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
|
||||
|
|
|
|||
Loading…
Reference in New Issue