Merge branch 'for-rmk/arm-mm-lpae' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into devel-stable
This series extends the existing ARM v2p runtime patching for 64 bit. Needed for LPAE machines which have physical memory beyond 4GB.
This commit is contained in:
Russell King
commit
8754c4bf2a
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@ -49,6 +49,7 @@ struct machine_desc {
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bool (*smp_init)(void);
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void (*fixup)(struct tag *, char **,
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struct meminfo *);
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void (*init_meminfo)(void);
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void (*reserve)(void);/* reserve mem blocks */
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void (*map_io)(void);/* IO mapping function */
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void (*init_early)(void);
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@ -172,8 +172,14 @@
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* so that all we need to do is modify the 8-bit constant field.
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*/
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#define __PV_BITS_31_24 0x81000000
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#define __PV_BITS_7_0 0x81
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extern phys_addr_t (*arch_virt_to_idmap) (unsigned long x);
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extern u64 __pv_phys_offset;
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extern u64 __pv_offset;
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extern void fixup_pv_table(const void *, unsigned long);
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extern const void *__pv_table_begin, *__pv_table_end;
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extern unsigned long __pv_phys_offset;
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#define PHYS_OFFSET __pv_phys_offset
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#define __pv_stub(from,to,instr,type) \
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@ -185,22 +191,58 @@ extern unsigned long __pv_phys_offset;
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: "=r" (to) \
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: "r" (from), "I" (type))
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static inline unsigned long __virt_to_phys(unsigned long x)
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#define __pv_stub_mov_hi(t) \
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__asm__ volatile("@ __pv_stub_mov\n" \
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"1: mov %R0, %1\n" \
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" .pushsection .pv_table,\"a\"\n" \
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" .long 1b\n" \
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" .popsection\n" \
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: "=r" (t) \
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: "I" (__PV_BITS_7_0))
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#define __pv_add_carry_stub(x, y) \
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__asm__ volatile("@ __pv_add_carry_stub\n" \
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"1: adds %Q0, %1, %2\n" \
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" adc %R0, %R0, #0\n" \
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" .pushsection .pv_table,\"a\"\n" \
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" .long 1b\n" \
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" .popsection\n" \
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: "+r" (y) \
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: "r" (x), "I" (__PV_BITS_31_24) \
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: "cc")
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static inline phys_addr_t __virt_to_phys(unsigned long x)
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{
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unsigned long t;
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__pv_stub(x, t, "add", __PV_BITS_31_24);
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phys_addr_t t;
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if (sizeof(phys_addr_t) == 4) {
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__pv_stub(x, t, "add", __PV_BITS_31_24);
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} else {
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__pv_stub_mov_hi(t);
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__pv_add_carry_stub(x, t);
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}
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return t;
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}
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static inline unsigned long __phys_to_virt(unsigned long x)
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static inline unsigned long __phys_to_virt(phys_addr_t x)
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{
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unsigned long t;
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__pv_stub(x, t, "sub", __PV_BITS_31_24);
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return t;
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}
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#else
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#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
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#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
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static inline phys_addr_t __virt_to_phys(unsigned long x)
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{
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return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
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}
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static inline unsigned long __phys_to_virt(phys_addr_t x)
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{
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return x - PHYS_OFFSET + PAGE_OFFSET;
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}
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#endif
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#endif
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#endif /* __ASSEMBLY__ */
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@ -238,16 +280,31 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
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static inline void *phys_to_virt(phys_addr_t x)
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{
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return (void *)(__phys_to_virt((unsigned long)(x)));
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return (void *)__phys_to_virt(x);
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}
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/*
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* Drivers should NOT use these either.
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*/
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#define __pa(x) __virt_to_phys((unsigned long)(x))
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#define __va(x) ((void *)__phys_to_virt((unsigned long)(x)))
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#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
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#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
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/*
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* These are for systems that have a hardware interconnect supported alias of
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* physical memory for idmap purposes. Most cases should leave these
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* untouched.
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*/
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static inline phys_addr_t __virt_to_idmap(unsigned long x)
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{
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if (arch_virt_to_idmap)
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return arch_virt_to_idmap(x);
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else
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return __virt_to_phys(x);
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}
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#define virt_to_idmap(x) __virt_to_idmap((unsigned long)(x))
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/*
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* Virtual <-> DMA view memory address translations
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* Again, these are *only* valid on the kernel direct mapped RAM
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@ -155,4 +155,5 @@ EXPORT_SYMBOL(__gnu_mcount_nc);
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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EXPORT_SYMBOL(__pv_phys_offset);
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EXPORT_SYMBOL(__pv_offset);
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#endif
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@ -536,6 +536,14 @@ ENTRY(fixup_smp)
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(fixup_smp)
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#ifdef __ARMEB_
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#define LOW_OFFSET 0x4
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#define HIGH_OFFSET 0x0
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#else
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#define LOW_OFFSET 0x0
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#define HIGH_OFFSET 0x4
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#endif
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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/* __fixup_pv_table - patch the stub instructions with the delta between
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@ -546,17 +554,20 @@ ENDPROC(fixup_smp)
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__HEAD
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__fixup_pv_table:
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adr r0, 1f
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ldmia r0, {r3-r5, r7}
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sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
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ldmia r0, {r3-r7}
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mvn ip, #0
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subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
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add r4, r4, r3 @ adjust table start address
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add r5, r5, r3 @ adjust table end address
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add r7, r7, r3 @ adjust __pv_phys_offset address
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str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
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add r6, r6, r3 @ adjust __pv_phys_offset address
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add r7, r7, r3 @ adjust __pv_offset address
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str r8, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_offset
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strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
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mov r6, r3, lsr #24 @ constant for add/sub instructions
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teq r3, r6, lsl #24 @ must be 16MiB aligned
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THUMB( it ne @ cross section branch )
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bne __error
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str r6, [r7, #4] @ save to __pv_offset
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str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
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b __fixup_a_pv_table
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ENDPROC(__fixup_pv_table)
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@ -565,10 +576,19 @@ ENDPROC(__fixup_pv_table)
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.long __pv_table_begin
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.long __pv_table_end
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2: .long __pv_phys_offset
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.long __pv_offset
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.text
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__fixup_a_pv_table:
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adr r0, 3f
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ldr r6, [r0]
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add r6, r6, r3
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ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
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ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
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mov r6, r6, lsr #24
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cmn r0, #1
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#ifdef CONFIG_THUMB2_KERNEL
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moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
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lsls r6, #24
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beq 2f
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clz r7, r6
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@ -582,18 +602,28 @@ __fixup_a_pv_table:
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b 2f
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1: add r7, r3
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ldrh ip, [r7, #2]
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and ip, 0x8f00
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orr ip, r6 @ mask in offset bits 31-24
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tst ip, #0x4000
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and ip, #0x8f00
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orrne ip, r6 @ mask in offset bits 31-24
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orreq ip, r0 @ mask in offset bits 7-0
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strh ip, [r7, #2]
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ldrheq ip, [r7]
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biceq ip, #0x20
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orreq ip, ip, r0, lsr #16
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strheq ip, [r7]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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bx lr
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#else
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moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
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b 2f
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1: ldr ip, [r7, r3]
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bic ip, ip, #0x000000ff
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orr ip, ip, r6 @ mask in offset bits 31-24
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tst ip, #0xf00 @ check the rotation field
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orrne ip, ip, r6 @ mask in offset bits 31-24
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biceq ip, ip, #0x400000 @ clear bit 22
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orreq ip, ip, r0 @ mask in offset bits 7-0
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str ip, [r7, r3]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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@ -602,28 +632,29 @@ __fixup_a_pv_table:
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#endif
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ENDPROC(__fixup_a_pv_table)
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3: .long __pv_offset
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ENTRY(fixup_pv_table)
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stmfd sp!, {r4 - r7, lr}
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ldr r2, 2f @ get address of __pv_phys_offset
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mov r3, #0 @ no offset
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mov r4, r0 @ r0 = table start
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add r5, r0, r1 @ r1 = table size
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ldr r6, [r2, #4] @ get __pv_offset
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bl __fixup_a_pv_table
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ldmfd sp!, {r4 - r7, pc}
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ENDPROC(fixup_pv_table)
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.align
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2: .long __pv_phys_offset
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.data
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.globl __pv_phys_offset
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.type __pv_phys_offset, %object
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__pv_phys_offset:
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.long 0
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.size __pv_phys_offset, . - __pv_phys_offset
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.quad 0
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.size __pv_phys_offset, . -__pv_phys_offset
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.globl __pv_offset
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.type __pv_offset, %object
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__pv_offset:
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.long 0
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.quad 0
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.size __pv_offset, . -__pv_offset
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#endif
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#include "head-common.S"
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@ -73,6 +73,8 @@ __setup("fpe=", fpe_setup);
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#endif
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extern void paging_init(const struct machine_desc *desc);
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extern void early_paging_init(const struct machine_desc *,
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struct proc_info_list *);
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extern void sanity_check_meminfo(void);
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extern enum reboot_mode reboot_mode;
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extern void setup_dma_zone(const struct machine_desc *desc);
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@ -878,6 +880,8 @@ void __init setup_arch(char **cmdline_p)
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parse_early_param();
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sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
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early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
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sanity_check_meminfo();
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arm_memblock_init(&meminfo, mdesc);
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@ -81,7 +81,7 @@ void __init smp_set_ops(struct smp_operations *ops)
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static unsigned long get_arch_pgd(pgd_t *pgd)
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{
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phys_addr_t pgdir = virt_to_phys(pgd);
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phys_addr_t pgdir = virt_to_idmap(pgd);
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BUG_ON(pgdir & ARCH_PGD_MASK);
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return pgdir >> ARCH_PGD_SHIFT;
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}
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@ -10,6 +10,7 @@
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#include <asm/system_info.h>
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pgd_t *idmap_pgd;
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phys_addr_t (*arch_virt_to_idmap) (unsigned long x);
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#ifdef CONFIG_ARM_LPAE
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static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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@ -67,8 +68,9 @@ static void identity_mapping_add(pgd_t *pgd, const char *text_start,
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unsigned long addr, end;
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unsigned long next;
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addr = virt_to_phys(text_start);
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end = virt_to_phys(text_end);
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addr = virt_to_idmap(text_start);
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end = virt_to_idmap(text_end);
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pr_info("Setting up static identity map for 0x%lx - 0x%lx\n", addr, end);
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prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
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@ -90,8 +92,6 @@ static int __init init_static_idmap(void)
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if (!idmap_pgd)
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return -ENOMEM;
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pr_info("Setting up static identity map for 0x%p - 0x%p\n",
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__idmap_text_start, __idmap_text_end);
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identity_mapping_add(idmap_pgd, __idmap_text_start,
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__idmap_text_end, 0);
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@ -28,6 +28,8 @@
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#include <asm/highmem.h>
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#include <asm/system_info.h>
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#include <asm/traps.h>
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#include <asm/procinfo.h>
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#include <asm/memory.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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@ -1315,6 +1317,86 @@ static void __init map_lowmem(void)
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}
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}
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#ifdef CONFIG_ARM_LPAE
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/*
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* early_paging_init() recreates boot time page table setup, allowing machines
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* to switch over to a high (>4G) address space on LPAE systems
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*/
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void __init early_paging_init(const struct machine_desc *mdesc,
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struct proc_info_list *procinfo)
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{
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pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
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unsigned long map_start, map_end;
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pgd_t *pgd0, *pgdk;
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pud_t *pud0, *pudk, *pud_start;
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pmd_t *pmd0, *pmdk;
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phys_addr_t phys;
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int i;
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if (!(mdesc->init_meminfo))
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return;
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/* remap kernel code and data */
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map_start = init_mm.start_code;
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map_end = init_mm.brk;
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/* get a handle on things... */
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pgd0 = pgd_offset_k(0);
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pud_start = pud0 = pud_offset(pgd0, 0);
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pmd0 = pmd_offset(pud0, 0);
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pgdk = pgd_offset_k(map_start);
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pudk = pud_offset(pgdk, map_start);
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pmdk = pmd_offset(pudk, map_start);
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mdesc->init_meminfo();
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/* Run the patch stub to update the constants */
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fixup_pv_table(&__pv_table_begin,
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(&__pv_table_end - &__pv_table_begin) << 2);
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/*
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* Cache cleaning operations for self-modifying code
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* We should clean the entries by MVA but running a
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* for loop over every pv_table entry pointer would
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* just complicate the code.
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*/
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flush_cache_louis();
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dsb();
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isb();
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/* remap level 1 table */
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for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
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set_pud(pud0,
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__pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
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pmd0 += PTRS_PER_PMD;
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}
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/* remap pmds for kernel mapping */
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phys = __pa(map_start) & PMD_MASK;
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do {
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*pmdk++ = __pmd(phys | pmdprot);
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phys += PMD_SIZE;
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} while (phys < map_end);
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flush_cache_all();
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cpu_switch_mm(pgd0, &init_mm);
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cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
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local_flush_bp_all();
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local_flush_tlb_all();
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}
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#else
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void __init early_paging_init(const struct machine_desc *mdesc,
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struct proc_info_list *procinfo)
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{
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if (mdesc->init_meminfo)
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mdesc->init_meminfo();
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}
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#endif
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/*
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* paging_init() sets up the page tables, initialises the zone memory
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* maps, and sets up the zero page, bad page and bad page tables.
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