ARM: EXYNOS: add clock part for EXYNOS5250 SoC
This patch adds clock-exynos5.c for EXYNOS5250 now and that can be used for other EXYNOS5 SoCs later. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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arch/arm/mach-exynos/clock-exynos5.c
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1247
arch/arm/mach-exynos/clock-exynos5.c
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@ -253,6 +253,68 @@
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#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
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/* For EXYNOS5250 */
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#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
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#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
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#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
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#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
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#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
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#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
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#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
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#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
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#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
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#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
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#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
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#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
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#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
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#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
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#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
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#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
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#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
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#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
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#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
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#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
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#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
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#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
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#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
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#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
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#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
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#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
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#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
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#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
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#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
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#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
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#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
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#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
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#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
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#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
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#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
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#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
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#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
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#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
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#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
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#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
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#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
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#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
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#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
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#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
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#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
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#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
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#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
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#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
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#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
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/* Compatibility defines and inclusion */
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#include <mach/regs-pmu.h>
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@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
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.id = -1,
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};
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/* BPLL clock output */
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struct clk clk_fout_bpll = {
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.name = "fout_bpll",
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.id = -1,
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};
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/* CPLL clock output */
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struct clk clk_fout_cpll = {
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.name = "fout_cpll",
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.id = -1,
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};
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/* MPLL clock output
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* No need .ctrlbit, this is always on
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*/
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@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
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.nr_sources = ARRAY_SIZE(clk_src_apll_list),
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};
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/* Possible clock sources for BPLL Mux */
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static struct clk *clk_src_bpll_list[] = {
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[0] = &clk_fin_bpll,
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[1] = &clk_fout_bpll,
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};
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struct clksrc_sources clk_src_bpll = {
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.sources = clk_src_bpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
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};
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/* Possible clock sources for CPLL Mux */
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static struct clk *clk_src_cpll_list[] = {
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[0] = &clk_fin_cpll,
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[1] = &clk_fout_cpll,
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};
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struct clksrc_sources clk_src_cpll = {
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.sources = clk_src_cpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_cpll_list),
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};
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/* Possible clock sources for MPLL Mux */
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static struct clk *clk_src_mpll_list[] = {
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[0] = &clk_fin_mpll,
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@ -18,6 +18,8 @@
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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#define clk_fin_apll clk_ext_xtal_mux
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#define clk_fin_bpll clk_ext_xtal_mux
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#define clk_fin_cpll clk_ext_xtal_mux
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#define clk_fin_mpll clk_ext_xtal_mux
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#define clk_fin_epll clk_ext_xtal_mux
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#define clk_fin_dpll clk_ext_xtal_mux
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@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
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extern struct clk clk_48m;
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extern struct clk s5p_clk_27m;
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extern struct clk clk_fout_apll;
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extern struct clk clk_fout_bpll;
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extern struct clk clk_fout_cpll;
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extern struct clk clk_fout_mpll;
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extern struct clk clk_fout_epll;
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extern struct clk clk_fout_dpll;
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@ -37,6 +41,8 @@ extern struct clk clk_arm;
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extern struct clk clk_vpll;
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extern struct clksrc_sources clk_src_apll;
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extern struct clksrc_sources clk_src_bpll;
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extern struct clksrc_sources clk_src_cpll;
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extern struct clksrc_sources clk_src_mpll;
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extern struct clksrc_sources clk_src_epll;
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extern struct clksrc_sources clk_src_dpll;
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