Merge tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel into drm-fixes
misc i915 fixes. * tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel: drm/i915: refine qemu south bridge detection drm/i915: Remove select to deleted STOP_MACHINE from Kconfig drm/i915: Fix NULL plane->fb oops on SKL drm/i915: Don't reject primary plane windowing with color keying enabled on SKL+ drm/i915/dp: fall back to 18 bpp when sink capability is unknown drm/i915: Make sure DC writes are coherent on flush.
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commit
87d0f93961
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@ -10,7 +10,6 @@ config DRM_I915
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# the shmem_readpage() which depends upon tmpfs
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# the shmem_readpage() which depends upon tmpfs
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select SHMEM
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select SHMEM
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select TMPFS
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select TMPFS
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select STOP_MACHINE
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select DRM_KMS_HELPER
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select DRM_KMS_HELPER
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select DRM_PANEL
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select DRM_PANEL
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select DRM_MIPI_DSI
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select DRM_MIPI_DSI
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@ -501,7 +501,9 @@ void intel_detect_pch(struct drm_device *dev)
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WARN_ON(!IS_SKYLAKE(dev) &&
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WARN_ON(!IS_SKYLAKE(dev) &&
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!IS_KABYLAKE(dev));
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!IS_KABYLAKE(dev));
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} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
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} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
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(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) {
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((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
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pch->subsystem_vendor == 0x1af4 &&
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pch->subsystem_device == 0x1100)) {
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dev_priv->pch_type = intel_virt_detect_pch(dev);
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dev_priv->pch_type = intel_virt_detect_pch(dev);
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} else
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} else
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continue;
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continue;
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@ -2946,7 +2946,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
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struct i915_vma *vma;
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struct i915_vma *vma;
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u64 offset;
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u64 offset;
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intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
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intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
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intel_plane->base.state);
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intel_plane->base.state);
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vma = i915_gem_obj_to_ggtt_view(obj, &view);
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vma = i915_gem_obj_to_ggtt_view(obj, &view);
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@ -12075,11 +12075,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
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pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
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pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
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}
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}
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/* Clamp bpp to 8 on screens without EDID 1.4 */
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/* Clamp bpp to default limit on screens without EDID 1.4 */
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if (connector->base.display_info.bpc == 0 && bpp > 24) {
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if (connector->base.display_info.bpc == 0) {
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DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
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int type = connector->base.connector_type;
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bpp);
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int clamp_bpp = 24;
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pipe_config->pipe_bpp = 24;
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/* Fall back to 18 bpp when DP sink capability is unknown. */
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if (type == DRM_MODE_CONNECTOR_DisplayPort ||
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type == DRM_MODE_CONNECTOR_eDP)
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clamp_bpp = 18;
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if (bpp > clamp_bpp) {
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DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
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bpp, clamp_bpp);
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pipe_config->pipe_bpp = clamp_bpp;
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}
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}
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}
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}
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}
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@ -13883,11 +13893,12 @@ intel_check_primary_plane(struct drm_plane *plane,
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int max_scale = DRM_PLANE_HELPER_NO_SCALING;
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int max_scale = DRM_PLANE_HELPER_NO_SCALING;
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bool can_position = false;
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bool can_position = false;
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/* use scaler when colorkey is not required */
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if (INTEL_INFO(plane->dev)->gen >= 9) {
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if (INTEL_INFO(plane->dev)->gen >= 9 &&
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/* use scaler when colorkey is not required */
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state->ckey.flags == I915_SET_COLORKEY_NONE) {
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if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
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min_scale = 1;
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min_scale = 1;
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max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
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max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
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}
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can_position = true;
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can_position = true;
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}
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}
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@ -1707,6 +1707,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
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if (flush_domains) {
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if (flush_domains) {
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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}
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}
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@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
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if (flush_domains) {
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if (flush_domains) {
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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}
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}
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if (invalidate_domains) {
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if (invalidate_domains) {
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@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
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if (flush_domains) {
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if (flush_domains) {
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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}
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}
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if (invalidate_domains) {
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if (invalidate_domains) {
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