drm/i915: Pass plane to vlv_compute_drain_latency()
Now that we have drm_planes for the cursor and primary we can move the pixel_size handling into vlv_compute_drain_latency() and just pass the appropriate plane to it. v2: Check plane->state->fb instead of plane->fb Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Resolve conflict with Matt's s/plane->fb/plane->state->fb/ patch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -755,16 +755,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
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}
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}
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static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
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static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
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int pixel_size)
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struct drm_plane *plane)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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int entries, prec_mult, drain_latency;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
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int entries, prec_mult, drain_latency, pixel_size;
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int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
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const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
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const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
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/*
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* FIXME the plane might have an fb
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* but be invisible (eg. due to clipping)
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*/
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if (!intel_crtc->active || !plane->state->fb)
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return 0;
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if (WARN(clock == 0, "Pixel clock is zero!\n"))
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if (WARN(clock == 0, "Pixel clock is zero!\n"))
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return 0;
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return 0;
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pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
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if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
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if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
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return 0;
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return 0;
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@ -798,31 +808,11 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pixel_size;
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enum pipe pipe = intel_crtc->pipe;
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enum pipe pipe = intel_crtc->pipe;
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struct vlv_wm_values wm = dev_priv->wm.vlv;
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struct vlv_wm_values wm = dev_priv->wm.vlv;
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wm.ddl[pipe].primary = 0;
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wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
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wm.ddl[pipe].cursor = 0;
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wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
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if (!intel_crtc_active(crtc)) {
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vlv_write_wm_values(intel_crtc, &wm);
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return;
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}
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/* Primary plane Drain Latency */
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pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; /* BPP */
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wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
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/* Cursor Drain Latency
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* BPP is always 4 for cursor
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*/
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pixel_size = 4;
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/* Program cursor DL only if it is enabled */
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if (intel_crtc->cursor_base)
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wm.ddl[pipe].cursor =
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vlv_compute_drain_latency(crtc, pixel_size);
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vlv_write_wm_values(intel_crtc, &wm);
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vlv_write_wm_values(intel_crtc, &wm);
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}
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}
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@ -989,7 +979,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane,
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if (enabled)
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if (enabled)
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wm.ddl[pipe].sprite[sprite] =
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wm.ddl[pipe].sprite[sprite] =
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vlv_compute_drain_latency(crtc, pixel_size);
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vlv_compute_drain_latency(crtc, plane);
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else
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else
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wm.ddl[pipe].sprite[sprite] = 0;
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wm.ddl[pipe].sprite[sprite] = 0;
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