KVM: PPC: Work around POWER7 DABR corruption problem
It turns out that on POWER7, writing to the DABR can cause a corrupted value to be written if the PMU is active and updating SDAR in continuous sampling mode. To work around this, we make sure that the PMU is inactive and SDAR updates are disabled (via MMCRA) when we are context-switching DABR. When the guest sets DABR via the H_SET_DABR hypercall, we use a slightly different workaround, which is to read back the DABR and write it again if it got corrupted. While we are at it, make it consistent that the saving and restoring of the guest's non-volatile GPRs and the FPRs are done with the guest setup of the PMU active. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>hifive-unleashed-5.1
Paul Mackerras
Avi Kivity
parent
7657f4089b
commit
8943633cf9
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@ -68,19 +68,24 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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rotldi r10,r10,16
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mtmsrd r10,1
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/* Save host PMU registers and load guest PMU registers */
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/* Save host PMU registers */
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/* R4 is live here (vcpu pointer) but not r3 or r5 */
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li r3, 1
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mfspr r7, SPRN_MMCR0 /* save MMCR0 */
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mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
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mfspr r6, SPRN_MMCRA
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BEGIN_FTR_SECTION
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/* On P7, clear MMCRA in order to disable SDAR updates */
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li r5, 0
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mtspr SPRN_MMCRA, r5
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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isync
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ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
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lbz r5, LPPACA_PMCINUSE(r3)
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cmpwi r5, 0
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beq 31f /* skip if not */
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mfspr r5, SPRN_MMCR1
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mfspr r6, SPRN_MMCRA
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std r7, HSTATE_MMCR(r13)
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std r5, HSTATE_MMCR + 8(r13)
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std r6, HSTATE_MMCR + 16(r13)
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@ -159,24 +159,15 @@ kvmppc_hv_entry:
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mflr r0
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std r0, HSTATE_VMHANDLER(r13)
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ld r14, VCPU_GPR(r14)(r4)
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ld r15, VCPU_GPR(r15)(r4)
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ld r16, VCPU_GPR(r16)(r4)
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ld r17, VCPU_GPR(r17)(r4)
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ld r18, VCPU_GPR(r18)(r4)
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ld r19, VCPU_GPR(r19)(r4)
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ld r20, VCPU_GPR(r20)(r4)
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ld r21, VCPU_GPR(r21)(r4)
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ld r22, VCPU_GPR(r22)(r4)
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ld r23, VCPU_GPR(r23)(r4)
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ld r24, VCPU_GPR(r24)(r4)
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ld r25, VCPU_GPR(r25)(r4)
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ld r26, VCPU_GPR(r26)(r4)
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ld r27, VCPU_GPR(r27)(r4)
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ld r28, VCPU_GPR(r28)(r4)
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ld r29, VCPU_GPR(r29)(r4)
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ld r30, VCPU_GPR(r30)(r4)
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ld r31, VCPU_GPR(r31)(r4)
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/* Set partition DABR */
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/* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
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li r5,3
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ld r6,VCPU_DABR(r4)
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mtspr SPRN_DABRX,r5
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mtspr SPRN_DABR,r6
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BEGIN_FTR_SECTION
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isync
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/* Load guest PMU registers */
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/* R4 is live here (vcpu pointer) */
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@ -215,6 +206,25 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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/* Load up FP, VMX and VSX registers */
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bl kvmppc_load_fp
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ld r14, VCPU_GPR(r14)(r4)
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ld r15, VCPU_GPR(r15)(r4)
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ld r16, VCPU_GPR(r16)(r4)
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ld r17, VCPU_GPR(r17)(r4)
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ld r18, VCPU_GPR(r18)(r4)
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ld r19, VCPU_GPR(r19)(r4)
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ld r20, VCPU_GPR(r20)(r4)
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ld r21, VCPU_GPR(r21)(r4)
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ld r22, VCPU_GPR(r22)(r4)
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ld r23, VCPU_GPR(r23)(r4)
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ld r24, VCPU_GPR(r24)(r4)
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ld r25, VCPU_GPR(r25)(r4)
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ld r26, VCPU_GPR(r26)(r4)
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ld r27, VCPU_GPR(r27)(r4)
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ld r28, VCPU_GPR(r28)(r4)
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ld r29, VCPU_GPR(r29)(r4)
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ld r30, VCPU_GPR(r30)(r4)
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ld r31, VCPU_GPR(r31)(r4)
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BEGIN_FTR_SECTION
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/* Switch DSCR to guest value */
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ld r5, VCPU_DSCR(r4)
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@ -256,12 +266,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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mtspr SPRN_DAR, r5
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mtspr SPRN_DSISR, r6
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/* Set partition DABR */
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li r5,3
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ld r6,VCPU_DABR(r4)
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mtspr SPRN_DABRX,r5
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mtspr SPRN_DABR,r6
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BEGIN_FTR_SECTION
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/* Restore AMR and UAMOR, set AMOR to all 1s */
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ld r5,VCPU_AMR(r4)
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@ -955,12 +959,6 @@ BEGIN_FTR_SECTION
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mtspr SPRN_AMR,r6
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/* Restore host DABR and DABRX */
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ld r5,HSTATE_DABR(r13)
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li r6,7
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mtspr SPRN_DABR,r5
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mtspr SPRN_DABRX,r6
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/* Switch DSCR back to host value */
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BEGIN_FTR_SECTION
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mfspr r8, SPRN_DSCR
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@ -999,6 +997,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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std r5, VCPU_SPRG2(r9)
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std r6, VCPU_SPRG3(r9)
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/* save FP state */
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mr r3, r9
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bl .kvmppc_save_fp
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/* Increment yield count if they have a VPA */
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ld r8, VCPU_VPA(r9) /* do they have a VPA? */
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cmpdi r8, 0
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@ -1013,6 +1015,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mfspr r4, SPRN_MMCR0 /* save MMCR0 */
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mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
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mfspr r6, SPRN_MMCRA
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BEGIN_FTR_SECTION
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/* On P7, clear MMCRA in order to disable SDAR updates */
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li r7, 0
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mtspr SPRN_MMCRA, r7
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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isync
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beq 21f /* if no VPA, save PMU stuff anyway */
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lbz r7, LPPACA_PMCINUSE(r8)
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@ -1021,7 +1029,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
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b 22f
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21: mfspr r5, SPRN_MMCR1
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mfspr r6, SPRN_MMCRA
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std r4, VCPU_MMCR(r9)
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std r5, VCPU_MMCR + 8(r9)
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std r6, VCPU_MMCR + 16(r9)
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@ -1046,17 +1053,20 @@ BEGIN_FTR_SECTION
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stw r11, VCPU_PMC + 28(r9)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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22:
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/* save FP state */
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mr r3, r9
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bl .kvmppc_save_fp
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/* Secondary threads go off to take a nap on POWER7 */
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BEGIN_FTR_SECTION
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lwz r0,VCPU_PTID(r3)
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lwz r0,VCPU_PTID(r9)
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cmpwi r0,0
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bne secondary_nap
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/* Restore host DABR and DABRX */
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ld r5,HSTATE_DABR(r13)
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li r6,7
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mtspr SPRN_DABR,r5
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mtspr SPRN_DABRX,r6
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/*
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* Reload DEC. HDEC interrupts were disabled when
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* we reloaded the host's LPCR value.
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@ -1393,7 +1403,12 @@ bounce_ext_interrupt:
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_GLOBAL(kvmppc_h_set_dabr)
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std r4,VCPU_DABR(r3)
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mtspr SPRN_DABR,r4
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/* Work around P7 bug where DABR can get corrupted on mtspr */
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1: mtspr SPRN_DABR,r4
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mfspr r5, SPRN_DABR
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cmpd r4, r5
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bne 1b
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isync
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li r3,0
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blr
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@ -1615,8 +1630,8 @@ kvm_no_guest:
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* r3 = vcpu pointer
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*/
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_GLOBAL(kvmppc_save_fp)
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mfmsr r9
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ori r8,r9,MSR_FP
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mfmsr r5
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ori r8,r5,MSR_FP
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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oris r8,r8,MSR_VEC@h
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@ -1665,7 +1680,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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mfspr r6,SPRN_VRSAVE
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stw r6,VCPU_VRSAVE(r3)
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mtmsrd r9
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mtmsrd r5
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isync
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blr
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