xtensa: disable IRQs while IRQ handler is running
IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.
This was overlooked in the commit
2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.
do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
hifive-unleashed-5.1
Max Filippov
Chris Zankel
parent
8f371c7521
commit
895666a992
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@ -354,16 +354,16 @@ common_exception:
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* so we can allow exceptions and interrupts (*) again.
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* Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
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*
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* (*) We only allow interrupts of higher priority than current IRQ
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* (*) We only allow interrupts if they were previously enabled and
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* we're not handling an IRQ
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*/
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rsr a3, ps
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addi a0, a0, -4
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movi a2, 1
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addi a0, a0, -EXCCAUSE_LEVEL1_INTERRUPT
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movi a2, LOCKLEVEL
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extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
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# a3 = PS.INTLEVEL
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movnez a2, a3, a3 # a2 = 1: level-1, > 1: high priority
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moveqz a3, a2, a0 # a3 = IRQ level iff interrupt
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moveqz a3, a2, a0 # a3 = LOCKLEVEL iff interrupt
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movi a2, 1 << PS_WOE_BIT
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or a3, a3, a2
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rsr a0, exccause
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@ -444,6 +444,8 @@ common_exception_return:
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1: l32i a3, a1, PT_PS
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_bbci.l a3, PS_UM_BIT, 4f
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rsil a2, 0
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/* Specific to a user exception exit:
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* We need to check some flags for signal handling and rescheduling,
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* and have to restore WB and WS, extra states, and all registers
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@ -684,51 +686,19 @@ common_exception_exit:
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l32i a0, a1, PT_DEPC
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l32i a3, a1, PT_AREG3
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_bltui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
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wsr a0, depc
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l32i a2, a1, PT_AREG2
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfde
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_bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
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1:
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/* Restore a0...a3 and return */
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rsr a0, ps
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extui a2, a0, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
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movi a0, 2f
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slli a2, a2, 4
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add a0, a2, a0
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l32i a2, a1, PT_AREG2
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jx a0
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.macro irq_exit_level level
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.align 16
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.if XCHAL_EXCM_LEVEL >= \level
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l32i a0, a1, PT_PC
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wsr a0, epc\level
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfi \level
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.endif
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.endm
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.align 16
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2:
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfe
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.align 16
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/* no rfi for level-1 irq, handled by rfe above*/
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nop
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irq_exit_level 2
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irq_exit_level 3
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irq_exit_level 4
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irq_exit_level 5
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irq_exit_level 6
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1: wsr a0, depc
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfde
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ENDPROC(kernel_exception)
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@ -196,7 +196,6 @@ void do_multihit(struct pt_regs *regs, unsigned long exccause)
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/*
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* IRQ handler.
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* PS.INTLEVEL is the current IRQ priority level.
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*/
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extern void do_IRQ(int, struct pt_regs *);
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@ -213,18 +212,21 @@ void do_interrupt(struct pt_regs *regs)
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XCHAL_INTLEVEL6_MASK,
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XCHAL_INTLEVEL7_MASK,
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};
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unsigned level = get_sr(ps) & PS_INTLEVEL_MASK;
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if (WARN_ON_ONCE(level >= ARRAY_SIZE(int_level_mask)))
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return;
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for (;;) {
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unsigned intread = get_sr(interrupt);
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unsigned intenable = get_sr(intenable);
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unsigned int_at_level = intread & intenable &
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int_level_mask[level];
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unsigned int_at_level = intread & intenable;
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unsigned level;
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if (!int_at_level)
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for (level = LOCKLEVEL; level > 0; --level) {
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if (int_at_level & int_level_mask[level]) {
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int_at_level &= int_level_mask[level];
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break;
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}
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}
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if (level == 0)
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return;
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/*
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@ -386,9 +386,12 @@ ENDPROC(_DebugInterruptVector)
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.if XCHAL_EXCM_LEVEL >= \level
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.section .Level\level\()InterruptVector.text, "ax"
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ENTRY(_Level\level\()InterruptVector)
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wsr a0, epc1
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wsr a0, excsave2
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rsr a0, epc\level
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xsr a0, epc1
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wsr a0, epc1
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movi a0, EXCCAUSE_LEVEL1_INTERRUPT
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wsr a0, exccause
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rsr a0, eps\level
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# branch to user or kernel vector
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j _SimulateUserKernelVectorException
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.endif
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@ -440,10 +443,8 @@ ENDPROC(_WindowOverflow4)
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*/
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.align 4
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_SimulateUserKernelVectorException:
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wsr a0, excsave2
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movi a0, 4 # LEVEL1_INTERRUPT cause
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wsr a0, exccause
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rsr a0, ps
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addi a0, a0, (1 << PS_EXCM_BIT)
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wsr a0, ps
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bbsi.l a0, PS_UM_BIT, 1f # branch if user mode
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rsr a0, excsave2 # restore a0
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j _KernelExceptionVector # simulate kernel vector exception
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