drm/i915/execlists: Split the atomic test_and_clear_bit for irq handler
Rather than impose the cost of a locked test before queuing a new request, reduce it to a simple test_bit() with a following clear_bit() prior to doing the CSB check. This ensure that if an interrupt does occur whilst reading from the CSB, we still detect it (the interrupt would trigger a rescheduling of the tasklet anyway). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/20170321113320.2603-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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@ -530,13 +530,18 @@ static void intel_lrc_irq_handler(unsigned long data)
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intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
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intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
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while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
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/* Prefer doing test_and_clear_bit() as a two stage operation to avoid
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* imposing the cost of a locked atomic transaction when submitting a
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* new request (outside of the context-switch interrupt).
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*/
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while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
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u32 __iomem *csb_mmio =
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u32 __iomem *csb_mmio =
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dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
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dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
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u32 __iomem *buf =
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u32 __iomem *buf =
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dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
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dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
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unsigned int csb, head, tail;
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unsigned int csb, head, tail;
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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csb = readl(csb_mmio);
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csb = readl(csb_mmio);
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head = GEN8_CSB_READ_PTR(csb);
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head = GEN8_CSB_READ_PTR(csb);
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tail = GEN8_CSB_WRITE_PTR(csb);
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tail = GEN8_CSB_WRITE_PTR(csb);
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