drm/radeon: update rptr saving logic for memory buffers
Add support for using memory buffers rather than scratch registers. Some rings may not be able to write to scratch registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -1364,17 +1364,25 @@ void evergreen_mc_program(struct radeon_device *rdev)
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void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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u32 next_rptr;
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/* set to DX10/11 mode */
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radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
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radeon_ring_write(ring, 1);
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if (ring->rptr_save_reg) {
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uint32_t next_rptr = ring->wptr + 3 + 4;
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next_rptr = ring->wptr + 3 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_CONFIG_REG_START) >> 2));
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radeon_ring_write(ring, next_rptr);
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} else if (rdev->wb.enabled) {
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next_rptr = ring->wptr + 5 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
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radeon_ring_write(ring, next_rptr);
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radeon_ring_write(ring, 0);
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}
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radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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@ -2163,10 +2163,12 @@ void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsign
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ring->ring_size = ring_size;
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ring->align_mask = 16 - 1;
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r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
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if (r) {
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DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
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ring->rptr_save_reg = 0;
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if (radeon_ring_supports_scratch_reg(rdev, ring)) {
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r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
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if (r) {
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DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
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ring->rptr_save_reg = 0;
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}
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}
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}
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@ -2576,13 +2578,21 @@ void r600_fini(struct radeon_device *rdev)
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void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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u32 next_rptr;
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if (ring->rptr_save_reg) {
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uint32_t next_rptr = ring->wptr + 3 + 4;
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next_rptr = ring->wptr + 3 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
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radeon_ring_write(ring, next_rptr);
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} else if (rdev->wb.enabled) {
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next_rptr = ring->wptr + 5 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
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radeon_ring_write(ring, next_rptr);
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radeon_ring_write(ring, 0);
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}
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radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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@ -623,6 +623,8 @@ struct radeon_ring {
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unsigned rptr_offs;
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unsigned rptr_reg;
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unsigned rptr_save_reg;
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u64 next_rptr_gpu_addr;
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volatile u32 *next_rptr_cpu_addr;
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unsigned wptr;
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unsigned wptr_old;
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unsigned wptr_reg;
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@ -758,6 +760,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev);
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void radeon_ib_pool_fini(struct radeon_device *rdev);
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int radeon_ib_ring_tests(struct radeon_device *rdev);
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/* Ring access between begin & end cannot sleep */
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bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
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int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
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int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
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@ -871,6 +875,7 @@ struct radeon_wb {
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};
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#define RADEON_WB_SCRATCH_OFFSET 0
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#define RADEON_WB_RING0_NEXT_RPTR 256
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#define RADEON_WB_CP_RPTR_OFFSET 1024
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#define RADEON_WB_CP1_RPTR_OFFSET 1280
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#define RADEON_WB_CP2_RPTR_OFFSET 1536
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@ -207,6 +207,19 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
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ring->ring_free_dw--;
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}
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bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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switch (ring->idx) {
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case RADEON_RING_TYPE_GFX_INDEX:
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case CAYMAN_RING_TYPE_CP1_INDEX:
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case CAYMAN_RING_TYPE_CP2_INDEX:
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return true;
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default:
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return false;
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}
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}
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void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 rptr;
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@ -372,7 +385,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
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mutex_lock(&rdev->ring_lock);
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*data = NULL;
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if (ring->ring_obj == NULL || !ring->rptr_save_reg) {
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if (ring->ring_obj == NULL) {
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mutex_unlock(&rdev->ring_lock);
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return 0;
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}
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@ -384,7 +397,16 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
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}
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/* calculate the number of dw on the ring */
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ptr = RREG32(ring->rptr_save_reg);
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if (ring->rptr_save_reg)
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ptr = RREG32(ring->rptr_save_reg);
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else if (rdev->wb.enabled)
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ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
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else {
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/* no way to read back the next rptr */
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mutex_unlock(&rdev->ring_lock);
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return 0;
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}
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size = ring->wptr + (ring->ring_size / 4);
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size -= ptr;
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size &= ring->ptr_mask;
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@ -478,6 +500,11 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
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}
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ring->ptr_mask = (ring->ring_size / 4) - 1;
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ring->ring_free_dw = ring->ring_size / 4;
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if (rdev->wb.enabled) {
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u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
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ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
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ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
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}
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if (radeon_debugfs_ring_init(rdev, ring)) {
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DRM_ERROR("Failed to register debugfs file for rings !\n");
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}
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@ -1772,12 +1772,20 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
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} else {
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u32 next_rptr;
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if (ring->rptr_save_reg) {
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uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
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next_rptr = ring->wptr + 3 + 4 + 8;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_CONFIG_REG_START) >> 2));
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radeon_ring_write(ring, next_rptr);
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} else if (rdev->wb.enabled) {
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next_rptr = ring->wptr + 5 + 4 + 8;
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (1 << 8));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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radeon_ring_write(ring, next_rptr);
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}
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header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
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