V4L/DVB (4553): Add support for saa7111 and partial support for saa7118
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>hifive-unleashed-5.1
Mauro Carvalho Chehab
parent
96ecfc4edf
commit
89f75ffc7e
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@ -1,4 +1,6 @@
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/* saa7115 - Philips SAA7113/SAA7114/SAA7115 video decoder driver
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/* saa711x - Philips SAA711x video decoder driver
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* This driver can work with saa7111, saa7111a, saa7113, saa7114,
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* saa7115 and saa7118.
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*
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* Based on saa7114 driver by Maxim Yevtyushkin, which is based on
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* the saa7111 driver by Dave Perks.
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@ -16,7 +18,9 @@
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* (2/17/2003)
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*
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* VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
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* SAA7113 support by Mauro Carvalho Chehab <mchehab@infradead.org>
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*
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* Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
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* SAA7111, SAA7113 and SAA7118 support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -44,7 +48,7 @@
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#include <media/saa7115.h>
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#include <asm/div64.h>
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MODULE_DESCRIPTION("Philips SAA7113/SAA7114/SAA7115 video decoder driver");
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MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
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MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
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"Hans Verkuil, Mauro Carvalho Chehab");
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MODULE_LICENSE("GPL");
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@ -55,8 +59,8 @@ module_param(debug, bool, 0644);
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MODULE_PARM_DESC(debug, "Debug level (0-1)");
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static unsigned short normal_i2c[] = {
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0x4a >> 1, 0x48 >> 1, /* SAA7113 */
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0x42 >> 1, 0x40 >> 1, /* SAA7114 and SAA7115 */
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0x4a >> 1, 0x48 >> 1, /* SAA7111, SAA7111A and SAA7113 */
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0x42 >> 1, 0x40 >> 1, /* SAA7114, SAA7115 and SAA7118 */
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I2C_CLIENT_END };
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@ -86,15 +90,58 @@ static inline int saa7115_write(struct i2c_client *client, u8 reg, u8 value)
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return i2c_smbus_write_byte_data(client, reg, value);
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}
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/* Sanity routine to check if a register is present */
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static int saa711x_has_reg(const int id, const u8 reg)
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{
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switch (id) {
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case V4L2_IDENT_SAA7111:
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if (reg>0x1f || reg==1 || reg==0x0f || reg==0x14 || reg==0x18
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|| reg==0x19 || reg==0x1d || reg==0x1e)
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return 0;
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case V4L2_IDENT_SAA7113:
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if (reg>0x62 || reg==0x14 || (reg>=0x18 && reg<=0x1e) ||
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(reg>=0x20 && reg<=0x3f) ||reg==0x5f )
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return 0;
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case V4L2_IDENT_SAA7114:
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if (reg>=0xf0 || (reg>=0x1a && reg<=0x1e) ||
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(reg>=0x20 && reg<=0x2f) ||
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(reg>=0x63 && reg<=0x7f) )
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return 0;
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case V4L2_IDENT_SAA7115:
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if ((reg>=0x20 && reg<=0x2f) || (reg==0x5c) ||
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(reg>=0xfc && reg<=0xfe) )
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return 0;
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case V4L2_IDENT_SAA7118:
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if (reg>=0xf0 || (reg>=0x1a && reg<=0x1d) ||
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(reg>=0x63 && reg<=0x6f) )
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return 0;
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}
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/* Those registers are reserved for all family */
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if (unlikely((reg>=0x20 && reg<=0x22) ||
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(reg>=0x26 && reg<=0x28) ||
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(reg>=0x3b && reg<=0x3f) || (reg==0x5f) ||
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(reg>=0x63 && reg<=0x6f) ) )
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return 0;
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return 1;
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}
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static int saa7115_writeregs(struct i2c_client *client, const unsigned char *regs)
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{
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struct saa7115_state *state = i2c_get_clientdata(client);
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unsigned char reg, data;
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while (*regs != 0x00) {
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reg = *(regs++);
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data = *(regs++);
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if (saa7115_write(client, reg, data) < 0)
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return -1;
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/* According with datasheets, reserved regs should be
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filled with 0 - seems better not to touch on they */
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if (saa711x_has_reg(state->ident,reg)) {
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if (saa7115_write(client, reg, data) < 0)
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return -1;
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}
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}
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return 0;
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}
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@ -106,10 +153,80 @@ static inline int saa7115_read(struct i2c_client *client, u8 reg)
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/* ----------------------------------------------------------------------- */
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/* SAA7111 initialization table */
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static const unsigned char saa7111_init_auto_input[] = {
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R_01_INC_DELAY, 0x00, /* reserved */
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/*front end */
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R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
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R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
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* GAFIX=0, GAI1=256, GAI2=256 */
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R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
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R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
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/* decoder */
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R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
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* pixels after end of last line */
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R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
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* work with NTSC, too */
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R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
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* VTRC=1, HPLL=0, VNOI=0 */
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R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
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* VBLB=0, UPTCV=0, APER=1 */
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R_0A_LUMA_BRIGHT_CNTL, 0x80,
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R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
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R_0C_CHROMA_SAT_CNTL, 0x40,
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R_0D_CHROMA_HUE_CNTL, 0x00,
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R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
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* FCTC=0, CHBW=1 */
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R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
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R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
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R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
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* OEYC=1, OEHV=1, VIPB=0, COLO=0 */
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R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
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R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
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R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
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R_15_VGATE_START_FID_CHG, 0x00,
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R_16_VGATE_STOP, 0x00,
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R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
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0x00, 0x00
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};
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/* SAA7113 init codes */
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static const unsigned char saa7113_init_auto_input[] = {
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R_01_INC_DELAY, 0x08,
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R_02_INPUT_CNTL_1, 0xc2,
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R_03_INPUT_CNTL_2, 0x30,
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R_04_INPUT_CNTL_3, 0x00,
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R_05_INPUT_CNTL_4, 0x00,
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R_06_H_SYNC_START, 0x89,
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R_07_H_SYNC_STOP, 0x0d,
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R_08_SYNC_CNTL, 0x88,
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R_09_LUMA_CNTL, 0x01,
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R_0A_LUMA_BRIGHT_CNTL, 0x80,
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R_0B_LUMA_CONTRAST_CNTL, 0x47,
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R_0C_CHROMA_SAT_CNTL, 0x40,
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R_0D_CHROMA_HUE_CNTL, 0x00,
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R_0E_CHROMA_CNTL_1, 0x01,
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R_0F_CHROMA_GAIN_CNTL, 0x2a,
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R_10_CHROMA_CNTL_2, 0x08,
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R_11_MODE_DELAY_CNTL, 0x0c,
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R_12_RT_SIGNAL_CNTL, 0x07,
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R_13_RT_X_PORT_OUT_CNTL, 0x00,
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R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
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R_15_VGATE_START_FID_CHG, 0x00,
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R_16_VGATE_STOP, 0x00,
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R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
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0x00, 0x00
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};
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/* If a value differs from the Hauppauge driver values, then the comment starts with
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'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
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Hauppauge driver sets. */
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/* SAA7114 and SAA7115 initialization table */
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static const unsigned char saa7115_init_auto_input[] = {
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/* Front-End Part */
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R_01_INC_DELAY, 0x48, /* white peak control disabled */
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@ -142,6 +259,7 @@ static const unsigned char saa7115_init_auto_input[] = {
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0x00, 0x00
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};
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/* Used to reset saa7113, saa7114 and saa7115 */
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static const unsigned char saa7115_cfg_reset_scaler[] = {
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R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
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R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
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@ -152,6 +270,7 @@ static const unsigned char saa7115_cfg_reset_scaler[] = {
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/* ============== SAA7715 VIDEO templates ============= */
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/* Used on saa7114 and saa7115 */
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static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
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/* hsize = 0x2d0 = 720 */
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R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
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@ -170,6 +289,7 @@ static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
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0x00, 0x00
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};
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/* Used on saa7114 and saa7115 */
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static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
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/* output window size = 248 (but 60hz is 240?) */
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R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
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@ -408,33 +528,6 @@ static const unsigned char saa7115_cfg_vbi_off[] = {
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0x00, 0x00
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};
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static const unsigned char saa7113_init_auto_input[] = {
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R_01_INC_DELAY, 0x08,
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R_02_INPUT_CNTL_1, 0xc2,
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R_03_INPUT_CNTL_2, 0x30,
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R_04_INPUT_CNTL_3, 0x00,
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R_05_INPUT_CNTL_4, 0x00,
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R_06_H_SYNC_START, 0x89,
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R_07_H_SYNC_STOP, 0x0d,
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R_08_SYNC_CNTL, 0x88,
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R_09_LUMA_CNTL, 0x01,
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R_0A_LUMA_BRIGHT_CNTL, 0x80,
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R_0B_LUMA_CONTRAST_CNTL, 0x47,
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R_0C_CHROMA_SAT_CNTL, 0x40,
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R_0D_CHROMA_HUE_CNTL, 0x00,
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R_0E_CHROMA_CNTL_1, 0x01,
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R_0F_CHROMA_GAIN_CNTL, 0x2a,
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R_10_CHROMA_CNTL_2, 0x08,
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R_11_MODE_DELAY_CNTL, 0x0c,
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R_12_RT_SIGNAL_CNTL, 0x07,
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R_13_RT_X_PORT_OUT_CNTL, 0x00,
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R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
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R_15_VGATE_START_FID_CHG, 0x00,
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R_16_VGATE_STOP, 0x00,
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R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
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0x00, 0x00
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};
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static const unsigned char saa7115_init_misc[] = {
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R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
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@ -662,7 +755,6 @@ static int saa7115_decode_wss(u8 * p)
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return wss;
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}
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static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
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{
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struct saa7115_state *state = i2c_get_clientdata(client);
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@ -672,16 +764,16 @@ static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
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u64 f;
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u8 acc = 0; /* reg 0x3a, audio clock control */
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/* Checks for chips that don't have audio clock (saa7111, saa7113) */
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if (!saa711x_has_reg(state->ident,R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
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return 0;
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v4l_dbg(1, debug, client, "set audio clock freq: %d\n", freq);
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/* sanity check */
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if (freq < 32000 || freq > 48000)
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return -EINVAL;
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/* The saa7113 has no audio clock */
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if (state->ident == V4L2_IDENT_SAA7113)
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return 0;
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/* hz is the refresh rate times 100 */
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hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
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/* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
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@ -799,7 +891,6 @@ static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *c
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static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
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{
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struct saa7115_state *state = i2c_get_clientdata(client);
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int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
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/* Prevent unnecessary standard changes. During a standard
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change the I-Port is temporarily disabled. Any devices
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@ -821,7 +912,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
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}
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/* Register 0E - Bits D6-D4 on NO-AUTO mode
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(SAA7113 doesn't have auto mode)
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(SAA7111 and SAA7113 doesn't have auto mode)
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50 Hz / 625 lines 60 Hz / 525 lines
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000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
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001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
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@ -829,7 +920,8 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
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011 NTSC N (3.58MHz) PAL M (3.58MHz)
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100 reserved NTSC-Japan (3.58MHz)
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*/
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if (state->ident == V4L2_IDENT_SAA7113) {
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if (state->ident == V4L2_IDENT_SAA7111 ||
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state->ident == V4L2_IDENT_SAA7113) {
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u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f;
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if (std == V4L2_STD_PAL_M) {
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@ -842,18 +934,19 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
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reg |= 0x40;
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}
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saa7115_write(client, R_0E_CHROMA_CNTL_1, reg);
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}
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} else {
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/* restart task B if needed */
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int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
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if (taskb && state->ident == V4L2_IDENT_SAA7114) {
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saa7115_writeregs(client, saa7115_cfg_vbi_on);
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}
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/* switch audio mode too! */
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saa7115_set_audio_clock_freq(client, state->audclk_freq);
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}
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state->std = std;
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/* restart task B if needed */
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if (taskb && state->ident != V4L2_IDENT_SAA7115) {
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saa7115_writeregs(client, saa7115_cfg_vbi_on);
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}
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/* switch audio mode too! */
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saa7115_set_audio_clock_freq(client, state->audclk_freq);
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}
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static v4l2_std_id saa7115_get_v4lstd(struct i2c_client *client)
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@ -919,9 +1012,16 @@ static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_fo
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u8 lcr[24];
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int i, x;
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/* saa7113/7114 doesn't yet support VBI */
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#if 1
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/* saa7113/7114/7118 VBI support are experimental */
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if (!saa711x_has_reg(state->ident,R_41_LCR_BASE))
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return;
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#else
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/* SAA7113 and SAA7118 also should support VBI - Need testing */
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if (state->ident != V4L2_IDENT_SAA7115)
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return;
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#endif
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for (i = 0; i <= 23; i++)
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lcr[i] = 0xff;
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@ -1021,8 +1121,9 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
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struct saa7115_state *state = i2c_get_clientdata(client);
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struct v4l2_pix_format *pix;
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int HPSC, HFSC;
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int VSCY, Vsrc;
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int VSCY;
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int is_50hz = state->std & V4L2_STD_625_50;
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int Vsrc = is_50hz ? 576 : 480;
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if (fmt->type == V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) {
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saa7115_set_lcr(client, &fmt->fmt.sliced);
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@ -1041,18 +1142,29 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
|
|||
if ((pix->height < 1) || (pix->height > 960))
|
||||
return -EINVAL;
|
||||
|
||||
if (!saa711x_has_reg(state->ident,R_D0_B_HORIZ_PRESCALING)) {
|
||||
/* Decoder only supports 720 columns and 480 or 576 lines */
|
||||
if (pix->width != 720)
|
||||
return -EINVAL;
|
||||
if (pix->height != Vsrc)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* probably have a valid size, let's set it */
|
||||
/* Set output width/height */
|
||||
/* width */
|
||||
saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
|
||||
(u8) (pix->width & 0xff));
|
||||
saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
|
||||
(u8) ((pix->width >> 8) & 0xff));
|
||||
/* height */
|
||||
saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
|
||||
(u8) (pix->height & 0xff));
|
||||
saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
|
||||
(u8) ((pix->height >> 8) & 0xff));
|
||||
|
||||
if (!saa711x_has_reg(state->ident,R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) {
|
||||
saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
|
||||
(u8) (pix->width & 0xff));
|
||||
saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
|
||||
(u8) ((pix->width >> 8) & 0xff));
|
||||
/* height */
|
||||
saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
|
||||
(u8) (pix->height & 0xff));
|
||||
saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
|
||||
(u8) ((pix->height >> 8) & 0xff));
|
||||
}
|
||||
|
||||
/* Scaling settings */
|
||||
/* Hprescaler is floor(inres/outres) */
|
||||
|
|
@ -1090,8 +1202,6 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
|
|||
}
|
||||
}
|
||||
|
||||
Vsrc = is_50hz ? 576 : 480;
|
||||
|
||||
if (pix->height != Vsrc) {
|
||||
VSCY = (int)((1024 * Vsrc) / pix->height);
|
||||
v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
|
||||
|
|
@ -1123,6 +1233,7 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
|
|||
}
|
||||
|
||||
saa7115_writeregs(client, saa7115_cfg_reset_scaler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1468,15 +1579,25 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
|
|||
state->hue = 0;
|
||||
state->sat = 64;
|
||||
switch (chip_id) {
|
||||
case 1:
|
||||
state->ident = V4L2_IDENT_SAA7111;
|
||||
break;
|
||||
case 3:
|
||||
state->ident = V4L2_IDENT_SAA7113;
|
||||
break;
|
||||
case 4:
|
||||
state->ident = V4L2_IDENT_SAA7114;
|
||||
break;
|
||||
default:
|
||||
case 5:
|
||||
state->ident = V4L2_IDENT_SAA7115;
|
||||
break;
|
||||
case 8:
|
||||
state->ident = V4L2_IDENT_SAA7118;
|
||||
break;
|
||||
default:
|
||||
state->ident = V4L2_IDENT_SAA7111;
|
||||
v4l_info(client, "WARNING: Chip is not known - Falling back to saa7111\n");
|
||||
|
||||
}
|
||||
|
||||
state->audclk_freq = 48000;
|
||||
|
|
@ -1484,7 +1605,8 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
|
|||
v4l_dbg(1, debug, client, "writing init values\n");
|
||||
|
||||
/* init to 60hz/48khz */
|
||||
if (state->ident == V4L2_IDENT_SAA7113) {
|
||||
if (state->ident == V4L2_IDENT_SAA7111 ||
|
||||
state->ident == V4L2_IDENT_SAA7113) {
|
||||
state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
|
||||
saa7115_writeregs(client, saa7113_init_auto_input);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -121,10 +121,17 @@ enum v4l2_chip_ident {
|
|||
/* general idents: reserved range 0-49 */
|
||||
V4L2_IDENT_UNKNOWN = 0,
|
||||
|
||||
/* module saa7115: reserved range 100-149 */
|
||||
/* module saa7110: just ident= 100 */
|
||||
V4L2_IDENT_SAA7110 = 100,
|
||||
|
||||
/* module saa7111: just ident= 101 */
|
||||
V4L2_IDENT_SAA7111 = 101,
|
||||
|
||||
/* module saa7115: reserved range 102-149 */
|
||||
V4L2_IDENT_SAA7113 = 103,
|
||||
V4L2_IDENT_SAA7114 = 104,
|
||||
V4L2_IDENT_SAA7115 = 105,
|
||||
V4L2_IDENT_SAA7118 = 108,
|
||||
|
||||
/* module saa7127: reserved range 150-199 */
|
||||
V4L2_IDENT_SAA7127 = 157,
|
||||
|
|
|
|||
Loading…
Reference in New Issue