powerpc/mm: Convert __hash_page_64K to C
Convert from asm to C Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Aneesh Kumar K.V
Michael Ellerman
parent
227fdbee5a
commit
89ff725051
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@ -40,7 +40,8 @@
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#define _PAGE_COMBO_VALID (_PAGE_F_GIX | _PAGE_F_SECOND)
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_F_SECOND | \
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_PAGE_F_GIX | _PAGE_HASHPTE | _PAGE_COMBO)
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/* Shift to put page number into pte.
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*
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@ -229,3 +229,133 @@ repeat:
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*ptep = __pte(new_pte & ~_PAGE_BUSY);
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return 0;
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}
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int __hash_page_64K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned long flags, int ssize)
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{
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unsigned long hpte_group;
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unsigned long rflags, pa;
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unsigned long old_pte, new_pte;
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unsigned long vpn, hash, slot;
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unsigned long shift = mmu_psize_defs[MMU_PAGE_64K].shift;
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/*
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* atomically mark the linux large page PTE busy and dirty
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*/
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do {
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pte_t pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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/* If PTE busy, retry the access */
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if (unlikely(old_pte & _PAGE_BUSY))
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return 0;
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/* If PTE permissions don't match, take page fault */
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if (unlikely(access & ~old_pte))
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return 1;
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/*
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* Check if PTE has the cache-inhibit bit set
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* If so, bail out and refault as a 4k page
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*/
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if (!mmu_has_feature(MMU_FTR_CI_LARGE_PAGE) &&
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unlikely(old_pte & _PAGE_NO_CACHE))
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return 0;
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/*
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* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access. Since this is 4K insert of 64K page size
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* also add _PAGE_COMBO
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*/
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new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
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if (access & _PAGE_RW)
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new_pte |= _PAGE_DIRTY;
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} while (old_pte != __cmpxchg_u64((unsigned long *)ptep,
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old_pte, new_pte));
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/*
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* PP bits. _PAGE_USER is already PP bit 0x2, so we only
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* need to add in 0x1 if it's a read-only user page
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*/
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rflags = new_pte & _PAGE_USER;
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if ((new_pte & _PAGE_USER) && !((new_pte & _PAGE_RW) &&
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(new_pte & _PAGE_DIRTY)))
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rflags |= 0x1;
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/*
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* _PAGE_EXEC -> HW_NO_EXEC since it's inverted
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*/
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rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
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/*
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* Always add C and Memory coherence bit
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*/
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rflags |= HPTE_R_C | HPTE_R_M;
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/*
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* Add in WIMG bits
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*/
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rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
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_PAGE_COHERENT | _PAGE_GUARDED));
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if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
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!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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vpn = hpt_vpn(ea, vsid, ssize);
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if (unlikely(old_pte & _PAGE_HASHPTE)) {
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/*
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* There MIGHT be an HPTE for this pte
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*/
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hash = hpt_hash(vpn, shift, ssize);
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if (old_pte & _PAGE_F_SECOND)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += (old_pte & _PAGE_F_GIX) >> _PAGE_F_GIX_SHIFT;
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if (ppc_md.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_64K,
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MMU_PAGE_64K, ssize, flags) == -1)
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old_pte &= ~_PAGE_HPTEFLAGS;
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}
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if (likely(!(old_pte & _PAGE_HASHPTE))) {
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
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hash = hpt_hash(vpn, shift, ssize);
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repeat:
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hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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/* Insert into the hash table, primary slot */
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slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
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MMU_PAGE_64K, MMU_PAGE_64K, ssize);
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/*
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* Primary is full, try the secondary
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*/
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if (unlikely(slot == -1)) {
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hpte_group = ((~hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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slot = ppc_md.hpte_insert(hpte_group, vpn, pa,
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rflags, HPTE_V_SECONDARY,
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MMU_PAGE_64K, MMU_PAGE_64K, ssize);
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if (slot == -1) {
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if (mftb() & 0x1)
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hpte_group = ((hash & htab_hash_mask) *
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HPTES_PER_GROUP) & ~0x7UL;
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ppc_md.hpte_remove(hpte_group);
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/*
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* FIXME!! Should be try the group from which we removed ?
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*/
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goto repeat;
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}
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}
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/*
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* Hypervisor failure. Restore old pmd and return -1
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* similar to __hash_page_*
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*/
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if (unlikely(slot == -2)) {
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*ptep = __pte(old_pte);
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hash_failure_debug(ea, access, vsid, trap, ssize,
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MMU_PAGE_64K, MMU_PAGE_64K, old_pte);
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return -1;
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}
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new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
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new_pte |= (slot << _PAGE_F_GIX_SHIFT) & (_PAGE_F_SECOND | _PAGE_F_GIX);
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}
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*ptep = __pte(new_pte & ~_PAGE_BUSY);
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return 0;
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}
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@ -328,292 +328,4 @@ htab_pte_insert_failure:
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li r3,-1
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b htab_bail
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#else /* CONFIG_PPC_64K_PAGES */
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/*****************************************************************************
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* *
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* 64K SW & 64K HW in a 64K segment pages implementation *
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* *
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*****************************************************************************/
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_GLOBAL(__hash_page_64K)
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mflr r0
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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/* Save all params that we need after a function call */
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std r6,STK_PARAM(R6)(r1)
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std r8,STK_PARAM(R8)(r1)
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std r9,STK_PARAM(R9)(r1)
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/* Save non-volatile registers.
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* r31 will hold "old PTE"
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* r30 is "new PTE"
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* r29 is vpn
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* r28 is a hash value
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* r27 is hashtab mask (maybe dynamic patched instead ?)
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*/
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std r27,STK_REG(R27)(r1)
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std r28,STK_REG(R28)(r1)
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std r29,STK_REG(R29)(r1)
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std r30,STK_REG(R30)(r1)
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std r31,STK_REG(R31)(r1)
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/* Step 1:
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*
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* Check permissions, atomically mark the linux PTE busy
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* and hashed.
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*/
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1:
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ldarx r31,0,r6
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/* Check access rights (access & ~(pte_val(*ptep))) */
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andc. r0,r4,r31
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bne- ht64_wrong_access
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/* Check if PTE is busy */
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andi. r0,r31,_PAGE_BUSY
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/* If so, just bail out and refault if needed. Someone else
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* is changing this PTE anyway and might hash it.
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*/
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bne- ht64_bail_ok
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BEGIN_FTR_SECTION
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/* Check if PTE has the cache-inhibit bit set */
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andi. r0,r31,_PAGE_NO_CACHE
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/* If so, bail out and refault as a 4k page */
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bne- ht64_bail_ok
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
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/* Prepare new PTE value (turn access RW into DIRTY, then
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* add BUSY and ACCESSED)
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*/
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rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
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or r30,r30,r31
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ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED
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/* Write the linux PTE atomically (setting busy) */
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stdcx. r30,0,r6
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bne- 1b
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isync
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/* Step 2:
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*
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* Insert/Update the HPTE in the hash table. At this point,
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* r4 (access) is re-useable, we use it for the new HPTE flags
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*/
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BEGIN_FTR_SECTION
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cmpdi r9,0 /* check segment size */
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bne 3f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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/* Calc vpn and put it in r29 */
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sldi r29,r5,SID_SHIFT - VPN_SHIFT
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rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
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or r29,r28,r29
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/* Calculate hash value for primary slot and store it in r28
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* r3 = va, r5 = vsid
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* r0 = (va >> 16) & ((1ul << (28 - 16)) -1)
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*/
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rldicl r0,r3,64-16,52
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xor r28,r5,r0 /* hash */
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b 4f
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3: /* Calc vpn and put it in r29 */
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sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
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rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
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or r29,r28,r29
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/*
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* calculate hash value for primary slot and
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* store it in r28 for 1T segment
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* r3 = va, r5 = vsid
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*/
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sldi r28,r5,25 /* vsid << 25 */
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/* r0 = (va >> 16) & ((1ul << (40 - 16)) -1) */
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rldicl r0,r3,64-16,40
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xor r28,r28,r5 /* vsid ^ ( vsid << 25) */
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xor r28,r28,r0 /* hash */
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/* Convert linux PTE bits into HW equivalents */
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4: andi. r3,r30,0x1fe /* Get basic set of flags */
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xori r3,r3,HPTE_R_N /* _PAGE_EXEC -> NOEXEC */
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rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
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rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
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andc r0,r30,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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ori r3,r3,HPTE_R_C | HPTE_R_M
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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*/
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BEGIN_FTR_SECTION
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mr r4,r30
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mr r5,r7
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bl hash_page_do_lazy_icache
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END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
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/* At this point, r3 contains new PP bits, save them in
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* place of "access" in the param area (sic)
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*/
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std r3,STK_PARAM(R4)(r1)
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/* Get htab_hash_mask */
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ld r4,htab_hash_mask@got(2)
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ld r27,0(r4) /* htab_hash_mask -> r27 */
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/* Check if we may already be in the hashtable, in this case, we
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* go to out-of-line code to try to modify the HPTE
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*/
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rldicl. r0,r31,64-12,48
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bne ht64_modify_pte
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ht64_insert_pte:
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/* Clear hpte bits in new pte (we also clear BUSY btw) and
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* add _PAGE_HPTE_SUB0
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*/
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lis r0,_PAGE_HPTEFLAGS@h
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ori r0,r0,_PAGE_HPTEFLAGS@l
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andc r30,r30,r0
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ori r30,r30,_PAGE_HASHPTE
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/* Phyical address in r5 */
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rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
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sldi r5,r5,PAGE_SHIFT
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/* Calculate primary group hash */
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and r0,r28,r27
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rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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/* Call ppc_md.hpte_insert */
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ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
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mr r4,r29 /* Retrieve vpn */
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li r7,0 /* !bolted, !secondary */
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li r8,MMU_PAGE_64K
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li r9,MMU_PAGE_64K /* actual page size */
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ld r10,STK_PARAM(R9)(r1) /* segment size */
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.globl ht64_call_hpte_insert1
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ht64_call_hpte_insert1:
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bl . /* patched by htab_finish_init() */
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cmpdi 0,r3,0
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bge ht64_pte_insert_ok /* Insertion successful */
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cmpdi 0,r3,-2 /* Critical failure */
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beq- ht64_pte_insert_failure
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/* Now try secondary slot */
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/* Phyical address in r5 */
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rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
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sldi r5,r5,PAGE_SHIFT
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/* Calculate secondary group hash */
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andc r0,r27,r28
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rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
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/* Call ppc_md.hpte_insert */
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ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
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mr r4,r29 /* Retrieve vpn */
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li r7,HPTE_V_SECONDARY /* !bolted, secondary */
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li r8,MMU_PAGE_64K
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li r9,MMU_PAGE_64K /* actual page size */
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ld r10,STK_PARAM(R9)(r1) /* segment size */
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.globl ht64_call_hpte_insert2
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ht64_call_hpte_insert2:
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bl . /* patched by htab_finish_init() */
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cmpdi 0,r3,0
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bge+ ht64_pte_insert_ok /* Insertion successful */
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cmpdi 0,r3,-2 /* Critical failure */
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beq- ht64_pte_insert_failure
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/* Both are full, we need to evict something */
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mftb r0
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/* Pick a random group based on TB */
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andi. r0,r0,1
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mr r5,r28
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bne 2f
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not r5,r5
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2: and r0,r5,r27
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rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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/* Call ppc_md.hpte_remove */
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.globl ht64_call_hpte_remove
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ht64_call_hpte_remove:
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bl . /* patched by htab_finish_init() */
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/* Try all again */
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b ht64_insert_pte
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ht64_bail_ok:
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li r3,0
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b ht64_bail
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ht64_pte_insert_ok:
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/* Insert slot number & secondary bit in PTE */
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rldimi r30,r3,12,63-15
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/* Write out the PTE with a normal write
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* (maybe add eieio may be good still ?)
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*/
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ht64_write_out_pte:
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ld r6,STK_PARAM(R6)(r1)
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std r30,0(r6)
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li r3, 0
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ht64_bail:
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ld r27,STK_REG(R27)(r1)
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ld r28,STK_REG(R28)(r1)
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ld r29,STK_REG(R29)(r1)
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ld r30,STK_REG(R30)(r1)
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ld r31,STK_REG(R31)(r1)
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addi r1,r1,STACKFRAMESIZE
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ld r0,16(r1)
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mtlr r0
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blr
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ht64_modify_pte:
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/* Keep PP bits in r4 and slot idx from the PTE around in r3 */
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mr r4,r3
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rlwinm r3,r31,32-12,29,31
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/* Secondary group ? if yes, get a inverted hash value */
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mr r5,r28
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andi. r0,r31,_PAGE_F_SECOND
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beq 1f
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not r5,r5
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1:
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/* Calculate proper slot value for ppc_md.hpte_updatepp */
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and r0,r5,r27
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rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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add r3,r0,r3 /* add slot idx */
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/* Call ppc_md.hpte_updatepp */
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mr r5,r29 /* vpn */
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li r6,MMU_PAGE_64K /* base page size */
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li r7,MMU_PAGE_64K /* actual page size */
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ld r8,STK_PARAM(R9)(r1) /* segment size */
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ld r9,STK_PARAM(R8)(r1) /* get "flags" param */
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.globl ht64_call_hpte_updatepp
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ht64_call_hpte_updatepp:
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bl . /* patched by htab_finish_init() */
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/* if we failed because typically the HPTE wasn't really here
|
||||
* we try an insertion.
|
||||
*/
|
||||
cmpdi 0,r3,-1
|
||||
beq- ht64_insert_pte
|
||||
|
||||
/* Clear the BUSY bit and Write out the PTE */
|
||||
li r0,_PAGE_BUSY
|
||||
andc r30,r30,r0
|
||||
b ht64_write_out_pte
|
||||
|
||||
ht64_wrong_access:
|
||||
/* Bail out clearing reservation */
|
||||
stdcx. r31,0,r6
|
||||
li r3,1
|
||||
b ht64_bail
|
||||
|
||||
ht64_pte_insert_failure:
|
||||
/* Bail out restoring old PTE */
|
||||
ld r6,STK_PARAM(R6)(r1)
|
||||
std r31,0(r6)
|
||||
li r3,-1
|
||||
b ht64_bail
|
||||
|
||||
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -633,28 +633,11 @@ extern u32 htab_call_hpte_insert1[];
|
|||
extern u32 htab_call_hpte_insert2[];
|
||||
extern u32 htab_call_hpte_remove[];
|
||||
extern u32 htab_call_hpte_updatepp[];
|
||||
extern u32 ht64_call_hpte_insert1[];
|
||||
extern u32 ht64_call_hpte_insert2[];
|
||||
extern u32 ht64_call_hpte_remove[];
|
||||
extern u32 ht64_call_hpte_updatepp[];
|
||||
|
||||
static void __init htab_finish_init(void)
|
||||
{
|
||||
#ifdef CONFIG_PPC_64K_PAGES
|
||||
patch_branch(ht64_call_hpte_insert1,
|
||||
ppc_function_entry(ppc_md.hpte_insert),
|
||||
BRANCH_SET_LINK);
|
||||
patch_branch(ht64_call_hpte_insert2,
|
||||
ppc_function_entry(ppc_md.hpte_insert),
|
||||
BRANCH_SET_LINK);
|
||||
patch_branch(ht64_call_hpte_remove,
|
||||
ppc_function_entry(ppc_md.hpte_remove),
|
||||
BRANCH_SET_LINK);
|
||||
patch_branch(ht64_call_hpte_updatepp,
|
||||
ppc_function_entry(ppc_md.hpte_updatepp),
|
||||
BRANCH_SET_LINK);
|
||||
#else /* !CONFIG_PPC_64K_PAGES */
|
||||
|
||||
#ifdef CONFIG_PPC_4K_PAGES
|
||||
patch_branch(htab_call_hpte_insert1,
|
||||
ppc_function_entry(ppc_md.hpte_insert),
|
||||
BRANCH_SET_LINK);
|
||||
|
|
|
|||
Loading…
Reference in New Issue