powerpc/32: Refactor EXCEPTION entry macros for head_8xx.S and head_32.S
EXCEPTION_PROLOG is similar in head_8xx.S and head_32.S This patch creates head_32.h and moves EXCEPTION_PROLOG macro into it. It also converts it from a GCC macro to a GAS macro in order to ease refactorisation with 40x later, since GAS macros allows the use of #ifdef/#else/#endif inside it. And it also has the advantage of not requiring the uggly "; \" at the end of each line. This patch also moves EXCEPTION() and EXC_XFER_XXXX() macros which are also similar while adding START_EXCEPTION() out of EXCEPTION(). Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.2
Christophe Leroy
Michael Ellerman
parent
e4dccf9092
commit
8a23fdec3d
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@ -37,6 +37,8 @@
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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#include "head_32.h"
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/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
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#define LOAD_BAT(n, reg, RA, RB) \
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/* see the comment for clear_bats() -- Cort */ \
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@ -246,103 +248,6 @@ __secondary_hold_spinloop:
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__secondary_hold_acknowledge:
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.long -1
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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* We assume sprg3 has the physical address of the current
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* task's thread_struct.
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*/
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#define EXCEPTION_PROLOG \
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mtspr SPRN_SPRG_SCRATCH0,r10; \
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mtspr SPRN_SPRG_SCRATCH1,r11; \
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mfcr r10; \
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EXCEPTION_PROLOG_1; \
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EXCEPTION_PROLOG_2
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#define EXCEPTION_PROLOG_1 \
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
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andi. r11,r11,MSR_PR; \
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tophys(r11,r1); /* use tophys(r1) if kernel */ \
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beq 1f; \
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mfspr r11,SPRN_SPRG_THREAD; \
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lwz r11,TASK_STACK-THREAD(r11); \
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addi r11,r11,THREAD_SIZE; \
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tophys(r11,r11); \
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1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
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#define EXCEPTION_PROLOG_2 \
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stw r10,_CCR(r11); /* save registers */ \
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stw r12,GPR12(r11); \
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stw r9,GPR9(r11); \
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mfspr r10,SPRN_SPRG_SCRATCH0; \
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stw r10,GPR10(r11); \
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mfspr r12,SPRN_SPRG_SCRATCH1; \
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stw r12,GPR11(r11); \
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mflr r10; \
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stw r10,_LINK(r11); \
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mfspr r12,SPRN_SRR0; \
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mfspr r9,SPRN_SRR1; \
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stw r1,GPR1(r11); \
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stw r1,0(r11); \
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tovirt(r1,r11); /* set new kernel sp */ \
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li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
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MTMSRD(r10); /* (except for mach check in rtas) */ \
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stw r0,GPR0(r11); \
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lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
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addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
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stw r10,8(r11); \
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SAVE_4GPRS(3, r11); \
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SAVE_2GPRS(7, r11)
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r11, r12 (SRR0), and r9 (SRR1).
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*
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* Note2: once we have set r1 we are in a position to take exceptions
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* again, and we could thus set MSR:RI at that point.
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*/
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/*
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* Exception vectors.
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*/
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#define EXCEPTION(n, label, hdlr, xfer) \
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. = n; \
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DO_KVM n; \
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label: \
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EXCEPTION_PROLOG; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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xfer(n, hdlr)
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#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
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li r10,trap; \
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stw r10,_TRAP(r11); \
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li r10,MSR_KERNEL; \
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copyee(r10, r9); \
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bl tfer; \
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i##n: \
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.long hdlr; \
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.long ret
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#define COPY_EE(d, s) rlwimi d,s,0,16,16
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#define NOCOPY(d, s)
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#define EXC_XFER_STD(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
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ret_from_except)
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#define EXC_XFER_EE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_EE_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
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ret_from_except)
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/* System reset */
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/* core99 pmac starts the seconary here by changing the vector, and
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putting it back to what it was (unknown_exception) when done. */
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@ -0,0 +1,118 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __HEAD_32_H__
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#define __HEAD_32_H__
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#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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* We assume sprg3 has the physical address of the current
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* task's thread_struct.
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*/
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.macro EXCEPTION_PROLOG
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mtspr SPRN_SPRG_SCRATCH0,r10
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mtspr SPRN_SPRG_SCRATCH1,r11
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mfcr r10
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2
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.endm
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.macro EXCEPTION_PROLOG_1
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mfspr r11,SPRN_SRR1 /* check whether user or kernel */
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andi. r11,r11,MSR_PR
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tophys(r11,r1) /* use tophys(r1) if kernel */
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beq 1f
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mfspr r11,SPRN_SPRG_THREAD
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lwz r11,TASK_STACK-THREAD(r11)
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addi r11,r11,THREAD_SIZE
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tophys(r11,r11)
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1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
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.endm
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.macro EXCEPTION_PROLOG_2
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stw r10,_CCR(r11) /* save registers */
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stw r12,GPR12(r11)
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stw r9,GPR9(r11)
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mfspr r10,SPRN_SPRG_SCRATCH0
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stw r10,GPR10(r11)
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mfspr r12,SPRN_SPRG_SCRATCH1
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stw r12,GPR11(r11)
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mflr r10
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stw r10,_LINK(r11)
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mfspr r12,SPRN_SRR0
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mfspr r9,SPRN_SRR1
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stw r1,GPR1(r11)
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stw r1,0(r11)
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tovirt(r1,r11) /* set new kernel sp */
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li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */
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MTMSRD(r10) /* (except for mach check in rtas) */
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stw r0,GPR0(r11)
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lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
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addi r10,r10,STACK_FRAME_REGS_MARKER@l
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stw r10,8(r11)
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SAVE_4GPRS(3, r11)
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SAVE_2GPRS(7, r11)
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.endm
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r11, r12 (SRR0), and r9 (SRR1).
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*
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* Note2: once we have set r1 we are in a position to take exceptions
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* again, and we could thus set MSR:RI at that point.
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*/
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/*
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* Exception vectors.
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*/
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#ifdef CONFIG_PPC_BOOK3S
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#define START_EXCEPTION(n, label) \
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. = n; \
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DO_KVM n; \
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label:
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#else
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#define START_EXCEPTION(n, label) \
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. = n; \
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label:
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#endif
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#define EXCEPTION(n, label, hdlr, xfer) \
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START_EXCEPTION(n, label) \
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EXCEPTION_PROLOG; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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xfer(n, hdlr)
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#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
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li r10,trap; \
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stw r10,_TRAP(r11); \
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li r10,MSR_KERNEL; \
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copyee(r10, r9); \
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bl tfer; \
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i##n: \
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.long hdlr; \
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.long ret
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#define COPY_EE(d, s) rlwimi d,s,0,MSR_EE
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#define NOCOPY(d, s)
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#define EXC_XFER_STD(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
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ret_from_except)
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#define EXC_XFER_EE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_EE_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
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ret_from_except)
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#endif /* __HEAD_32_H__ */
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@ -33,6 +33,8 @@
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#include <asm/export.h>
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#include <asm/code-patching-asm.h>
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#include "head_32.h"
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#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
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/* By simply checking Address >= 0x80000000, we know if its a kernel address */
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#define SIMPLE_KERNEL_ADDRESS 1
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@ -123,102 +125,6 @@ instruction_counter:
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.space 4
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#endif
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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* We assume sprg3 has the physical address of the current
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* task's thread_struct.
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*/
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#define EXCEPTION_PROLOG \
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mtspr SPRN_SPRG_SCRATCH0, r10; \
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mtspr SPRN_SPRG_SCRATCH1, r11; \
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mfcr r10; \
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EXCEPTION_PROLOG_1; \
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EXCEPTION_PROLOG_2
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#define EXCEPTION_PROLOG_1 \
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
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andi. r11,r11,MSR_PR; \
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tophys(r11,r1); /* use tophys(r1) if kernel */ \
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beq 1f; \
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mfspr r11,SPRN_SPRG_THREAD; \
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lwz r11,TASK_STACK-THREAD(r11); \
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addi r11,r11,THREAD_SIZE; \
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tophys(r11,r11); \
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1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
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#define EXCEPTION_PROLOG_2 \
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stw r10,_CCR(r11); /* save registers */ \
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stw r12,GPR12(r11); \
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stw r9,GPR9(r11); \
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mfspr r10,SPRN_SPRG_SCRATCH0; \
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stw r10,GPR10(r11); \
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mfspr r12,SPRN_SPRG_SCRATCH1; \
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stw r12,GPR11(r11); \
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mflr r10; \
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stw r10,_LINK(r11); \
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mfspr r12,SPRN_SRR0; \
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mfspr r9,SPRN_SRR1; \
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stw r1,GPR1(r11); \
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stw r1,0(r11); \
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tovirt(r1,r11); /* set new kernel sp */ \
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li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
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mtmsr r10; \
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stw r0,GPR0(r11); \
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lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
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addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
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stw r10, 8(r11); \
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SAVE_4GPRS(3, r11); \
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SAVE_2GPRS(7, r11)
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r11, r12 (SRR0), and r9 (SRR1).
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*
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* Note2: once we have set r1 we are in a position to take exceptions
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* again, and we could thus set MSR:RI at that point.
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*/
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/*
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* Exception vectors.
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*/
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#define EXCEPTION(n, label, hdlr, xfer) \
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. = n; \
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label: \
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EXCEPTION_PROLOG; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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xfer(n, hdlr)
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#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
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li r10,trap; \
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stw r10,_TRAP(r11); \
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li r10,MSR_KERNEL; \
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copyee(r10, r9); \
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bl tfer; \
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i##n: \
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.long hdlr; \
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.long ret
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#define COPY_EE(d, s) rlwimi d,s,0,16,16
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#define NOCOPY(d, s)
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#define EXC_XFER_STD(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
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ret_from_except)
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#define EXC_XFER_EE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_EE_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
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ret_from_except)
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/* System reset */
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EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
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