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arm64: dts: add partition reset function for i.MX8QM/QXP 

Add partition reset function for i.MX8QM/QXP.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Clark Wang 2019-08-20 21:18:19 +08:00 committed by Dong Aisheng
parent 12e3cb0ed3
commit 8a47ddc5e1
6 changed files with 361 additions and 2 deletions
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5
arch/arm64/boot/dts/freescale/Makefile
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@ -31,7 +31,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-max9286.dtb \
imx8qm-mek-enet2-tja1100.dtb
imx8qm-mek-enet2-tja1100.dtb imx8qm-mek-rpmsg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-max9286.dtb \
imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb
imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \
imx8qxp-mek-rpmsg.dtb

35
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
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@ -441,4 +441,39 @@ dma_subsys: bus@5a000000 {
"can0_lpcg_chi_clk";
power-domains = <&pd IMX_SC_R_CAN_0>;
};
i2c_rpbus_0: i2c-rpbus-0 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_1: i2c-rpbus-1 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_5: i2c-rpbus-5 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_12: i2c-rpbus-12 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_13: i2c-rpbus-13 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_14: i2c-rpbus-14 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
i2c_rpbus_15: i2c-rpbus-15 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
};

79
arch/arm64/boot/dts/freescale/imx8qm-mek-rpmsg.dts 100644
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@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2019
#include "imx8qm-mek.dts"
/delete-node/ &cm41_i2c;
&i2c_rpbus_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&cm41_i2c_lpcg {
status = "disabled";
};
&reg_can01_en {
status = "disabled";
};
&reg_can2_en {
status = "disabled";
};
&reg_can01_stby {
status = "disabled";
};
&reg_can2_stby {
status = "disabled";
};
&cm41_intmux {
status = "disabled";
};
&can0_lpcg {
status = "disabled";
};
&can1_lpcg {
status = "disabled";
};
&can2_lpcg {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&flexcan3 {
status = "disabled";
};
&flexspi0 {
status = "disabled";
};
&lpuart2 {
status = "disabled";
};
&uart2_lpcg {
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -44,6 +44,8 @@
dpu1 = &dpu2;
ldb0 = &ldb1;
ldb1 = &ldb2;
i2c0 = &i2c_rpbus_0;
i2c1 = &i2c_rpbus_1;
};
cpus {

236
arch/arm64/boot/dts/freescale/imx8qxp-mek-rpmsg.dts 100755
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@ -0,0 +1,236 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2019
#include "imx8qxp-mek.dts"
/delete-node/ &cm40_i2c;
/delete-node/ &i2c1;
&i2c_rpbus_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
interrupt-parent = <&lsio_gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "source";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&i2c_rpbus_5 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
wlf,shared-lrclk;
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_b 1 GPIO_ACTIVE_HIGH>;
power-domains = <&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>;
power-domain-names = "pd_mclk_out_0",
"pd_audio_clk_0",
"pd_audio_clk_1",
"pd_audio_clk_0",
"pd_audio_clk_1";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
fsl,txs-rxm;
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_parallel_csi>;
clocks = <&pi0_misc_lpcg 0>;
assigned-clocks = <&pi0_misc_lpcg 0>;
assigned-clock-rates = <24000000>;
clock-names = "xclk";
powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&parallel_csi_ep>;
bus-type = <5>; /* V4L2_FWNODE_BUS_TYPE_PARALLEL */
bus-width = <8>;
vsync-active = <0>;
hsync-active = <1>;
pclk-sample = <1>;
};
};
};
};
&i2c_rpbus_12 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c_rpbus_14 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
interrupt-open-drain;
};
fxas2100x@21 {
compatible = "fsl,fxas2100x";
reg = <0x21>;
interrupt-open-drain;
};
pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
&i2c_rpbus_15 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca9557_a: gpio@1a {
compatible = "nxp,pca9557";
reg = <0x1a>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@1d {
compatible = "nxp,pca9557";
reg = <0x1d>;
gpio-controller;
#gpio-cells = <2>;
};
isl29023@44 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isl29023>;
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&lsio_gpio1>;
interrupts = <2 2>;
};
};
&cm40_i2c_lpcg {
status = "disabled";
};
&i2c1_lpcg {
status = "disabled";
};
&can0_lpcg {
status = "disabled";
};
&reg_can_en {
status = "disabled";
};
&reg_can_stby {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&cm40_intmux {
status = "disabled";
};
&flexspi0 {
status = "disabled";
};
&lpuart3 {
status = "disabled";
};
&uart3_lpcg {
status = "disabled";
};

6
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -50,6 +50,12 @@
can0 = &flexcan1;
can1 = &flexcan2;
can2 = &flexcan3;
i2c1 = &i2c_rpbus_1;
i2c5 = &i2c_rpbus_5;
i2c12 = &i2c_rpbus_12;
i2c13 = &i2c_rpbus_13;
i2c14 = &i2c_rpbus_14;
i2c15 = &i2c_rpbus_15;
};
cpus {