Merge branch 'amd-iommu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu into x86/urgent
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8a4a6182fd
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@ -29,9 +29,11 @@ extern void amd_iommu_detect(void);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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extern void amd_iommu_flush_all_domains(void);
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extern void amd_iommu_flush_all_devices(void);
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extern void amd_iommu_shutdown(void);
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#else
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static inline int amd_iommu_init(void) { return -ENODEV; }
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static inline void amd_iommu_detect(void) { }
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static inline void amd_iommu_shutdown(void) { }
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#endif
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#endif /* _ASM_X86_AMD_IOMMU_H */
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@ -434,6 +434,16 @@ static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
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iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
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}
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/* Flush the whole IO/TLB for a given protection domain - including PDE */
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static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
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{
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u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
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INC_STATS_COUNTER(domain_flush_single);
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iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
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}
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/*
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* This function is used to flush the IO/TLB for a given protection domain
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* on every IOMMU in the system
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@ -1078,7 +1088,13 @@ static void attach_device(struct amd_iommu *iommu,
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amd_iommu_pd_table[devid] = domain;
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write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
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/*
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* We might boot into a crash-kernel here. The crashed kernel
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* left the caches in the IOMMU dirty. So we have to flush
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* here to evict all dirty stuff.
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*/
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iommu_queue_inv_dev_entry(iommu, devid);
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iommu_flush_tlb_pde(iommu, domain->id);
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}
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/*
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@ -260,6 +260,14 @@ static void iommu_enable(struct amd_iommu *iommu)
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static void iommu_disable(struct amd_iommu *iommu)
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{
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/* Disable command buffer */
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iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
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/* Disable event logging and event interrupts */
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iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
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iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
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/* Disable IOMMU hardware itself */
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iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
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}
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@ -478,6 +486,10 @@ static void iommu_enable_event_buffer(struct amd_iommu *iommu)
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memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
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&entry, sizeof(entry));
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/* set head and tail to zero manually */
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writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
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writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
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iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
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}
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@ -1042,6 +1054,7 @@ static void enable_iommus(void)
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struct amd_iommu *iommu;
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for_each_iommu(iommu) {
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iommu_disable(iommu);
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iommu_set_device_table(iommu);
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iommu_enable_command_buffer(iommu);
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iommu_enable_event_buffer(iommu);
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@ -1066,12 +1079,6 @@ static void disable_iommus(void)
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static int amd_iommu_resume(struct sys_device *dev)
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{
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/*
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* Disable IOMMUs before reprogramming the hardware registers.
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* IOMMU is still enabled from the resume kernel.
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*/
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disable_iommus();
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/* re-load the hardware */
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enable_iommus();
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@ -1079,8 +1086,8 @@ static int amd_iommu_resume(struct sys_device *dev)
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* we have to flush after the IOMMUs are enabled because a
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* disabled IOMMU will never execute the commands we send
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*/
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amd_iommu_flush_all_domains();
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amd_iommu_flush_all_devices();
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amd_iommu_flush_all_domains();
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return 0;
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}
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@ -1273,6 +1280,11 @@ free:
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goto out;
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}
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void amd_iommu_shutdown(void)
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{
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disable_iommus();
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}
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/****************************************************************************
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*
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* Early detect code. This code runs at IOMMU detection time in the DMA
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@ -27,6 +27,7 @@
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#include <asm/cpu.h>
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#include <asm/reboot.h>
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#include <asm/virtext.h>
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#include <asm/iommu.h>
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#if defined(CONFIG_SMP) && defined(CONFIG_X86_LOCAL_APIC)
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@ -103,5 +104,10 @@ void native_machine_crash_shutdown(struct pt_regs *regs)
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#ifdef CONFIG_HPET_TIMER
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hpet_disable();
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#endif
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#ifdef CONFIG_X86_64
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pci_iommu_shutdown();
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#endif
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crash_save_cpu(regs, safe_smp_processor_id());
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}
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@ -290,6 +290,8 @@ static int __init pci_iommu_init(void)
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void pci_iommu_shutdown(void)
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{
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gart_iommu_shutdown();
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amd_iommu_shutdown();
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}
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/* Must execute after PCI subsystem */
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fs_initcall(pci_iommu_init);
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