drm/radeon/kms: add support for MC ucode loading on SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
0f0de06c80
commit
8b074dd640
|
|
@ -77,6 +77,201 @@ int si_get_temp(struct radeon_device *rdev)
|
|||
return actual_temp;
|
||||
}
|
||||
|
||||
#define TAHITI_IO_MC_REGS_SIZE 36
|
||||
|
||||
static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
|
||||
{0x0000006f, 0x03044000},
|
||||
{0x00000070, 0x0480c018},
|
||||
{0x00000071, 0x00000040},
|
||||
{0x00000072, 0x01000000},
|
||||
{0x00000074, 0x000000ff},
|
||||
{0x00000075, 0x00143400},
|
||||
{0x00000076, 0x08ec0800},
|
||||
{0x00000077, 0x040000cc},
|
||||
{0x00000079, 0x00000000},
|
||||
{0x0000007a, 0x21000409},
|
||||
{0x0000007c, 0x00000000},
|
||||
{0x0000007d, 0xe8000000},
|
||||
{0x0000007e, 0x044408a8},
|
||||
{0x0000007f, 0x00000003},
|
||||
{0x00000080, 0x00000000},
|
||||
{0x00000081, 0x01000000},
|
||||
{0x00000082, 0x02000000},
|
||||
{0x00000083, 0x00000000},
|
||||
{0x00000084, 0xe3f3e4f4},
|
||||
{0x00000085, 0x00052024},
|
||||
{0x00000087, 0x00000000},
|
||||
{0x00000088, 0x66036603},
|
||||
{0x00000089, 0x01000000},
|
||||
{0x0000008b, 0x1c0a0000},
|
||||
{0x0000008c, 0xff010000},
|
||||
{0x0000008e, 0xffffefff},
|
||||
{0x0000008f, 0xfff3efff},
|
||||
{0x00000090, 0xfff3efbf},
|
||||
{0x00000094, 0x00101101},
|
||||
{0x00000095, 0x00000fff},
|
||||
{0x00000096, 0x00116fff},
|
||||
{0x00000097, 0x60010000},
|
||||
{0x00000098, 0x10010000},
|
||||
{0x00000099, 0x00006000},
|
||||
{0x0000009a, 0x00001000},
|
||||
{0x0000009f, 0x00a77400}
|
||||
};
|
||||
|
||||
static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
|
||||
{0x0000006f, 0x03044000},
|
||||
{0x00000070, 0x0480c018},
|
||||
{0x00000071, 0x00000040},
|
||||
{0x00000072, 0x01000000},
|
||||
{0x00000074, 0x000000ff},
|
||||
{0x00000075, 0x00143400},
|
||||
{0x00000076, 0x08ec0800},
|
||||
{0x00000077, 0x040000cc},
|
||||
{0x00000079, 0x00000000},
|
||||
{0x0000007a, 0x21000409},
|
||||
{0x0000007c, 0x00000000},
|
||||
{0x0000007d, 0xe8000000},
|
||||
{0x0000007e, 0x044408a8},
|
||||
{0x0000007f, 0x00000003},
|
||||
{0x00000080, 0x00000000},
|
||||
{0x00000081, 0x01000000},
|
||||
{0x00000082, 0x02000000},
|
||||
{0x00000083, 0x00000000},
|
||||
{0x00000084, 0xe3f3e4f4},
|
||||
{0x00000085, 0x00052024},
|
||||
{0x00000087, 0x00000000},
|
||||
{0x00000088, 0x66036603},
|
||||
{0x00000089, 0x01000000},
|
||||
{0x0000008b, 0x1c0a0000},
|
||||
{0x0000008c, 0xff010000},
|
||||
{0x0000008e, 0xffffefff},
|
||||
{0x0000008f, 0xfff3efff},
|
||||
{0x00000090, 0xfff3efbf},
|
||||
{0x00000094, 0x00101101},
|
||||
{0x00000095, 0x00000fff},
|
||||
{0x00000096, 0x00116fff},
|
||||
{0x00000097, 0x60010000},
|
||||
{0x00000098, 0x10010000},
|
||||
{0x00000099, 0x00006000},
|
||||
{0x0000009a, 0x00001000},
|
||||
{0x0000009f, 0x00a47400}
|
||||
};
|
||||
|
||||
static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
|
||||
{0x0000006f, 0x03044000},
|
||||
{0x00000070, 0x0480c018},
|
||||
{0x00000071, 0x00000040},
|
||||
{0x00000072, 0x01000000},
|
||||
{0x00000074, 0x000000ff},
|
||||
{0x00000075, 0x00143400},
|
||||
{0x00000076, 0x08ec0800},
|
||||
{0x00000077, 0x040000cc},
|
||||
{0x00000079, 0x00000000},
|
||||
{0x0000007a, 0x21000409},
|
||||
{0x0000007c, 0x00000000},
|
||||
{0x0000007d, 0xe8000000},
|
||||
{0x0000007e, 0x044408a8},
|
||||
{0x0000007f, 0x00000003},
|
||||
{0x00000080, 0x00000000},
|
||||
{0x00000081, 0x01000000},
|
||||
{0x00000082, 0x02000000},
|
||||
{0x00000083, 0x00000000},
|
||||
{0x00000084, 0xe3f3e4f4},
|
||||
{0x00000085, 0x00052024},
|
||||
{0x00000087, 0x00000000},
|
||||
{0x00000088, 0x66036603},
|
||||
{0x00000089, 0x01000000},
|
||||
{0x0000008b, 0x1c0a0000},
|
||||
{0x0000008c, 0xff010000},
|
||||
{0x0000008e, 0xffffefff},
|
||||
{0x0000008f, 0xfff3efff},
|
||||
{0x00000090, 0xfff3efbf},
|
||||
{0x00000094, 0x00101101},
|
||||
{0x00000095, 0x00000fff},
|
||||
{0x00000096, 0x00116fff},
|
||||
{0x00000097, 0x60010000},
|
||||
{0x00000098, 0x10010000},
|
||||
{0x00000099, 0x00006000},
|
||||
{0x0000009a, 0x00001000},
|
||||
{0x0000009f, 0x00a37400}
|
||||
};
|
||||
|
||||
/* ucode loading */
|
||||
static int si_mc_load_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
const __be32 *fw_data;
|
||||
u32 running, blackout = 0;
|
||||
u32 *io_mc_regs;
|
||||
int i, ucode_size, regs_size;
|
||||
|
||||
if (!rdev->mc_fw)
|
||||
return -EINVAL;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_TAHITI:
|
||||
io_mc_regs = (u32 *)&tahiti_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
case CHIP_VERDE:
|
||||
default:
|
||||
io_mc_regs = (u32 *)&verde_io_mc_regs;
|
||||
ucode_size = SI_MC_UCODE_SIZE;
|
||||
regs_size = TAHITI_IO_MC_REGS_SIZE;
|
||||
break;
|
||||
}
|
||||
|
||||
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
|
||||
|
||||
if (running == 0) {
|
||||
if (running) {
|
||||
blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
|
||||
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
|
||||
}
|
||||
|
||||
/* reset the engine and set to writable */
|
||||
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
|
||||
WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
|
||||
|
||||
/* load mc io regs */
|
||||
for (i = 0; i < regs_size; i++) {
|
||||
WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
|
||||
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
|
||||
}
|
||||
/* load the MC ucode */
|
||||
fw_data = (const __be32 *)rdev->mc_fw->data;
|
||||
for (i = 0; i < ucode_size; i++)
|
||||
WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
|
||||
|
||||
/* put the engine back into the active state */
|
||||
WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
|
||||
WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
|
||||
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
|
||||
|
||||
/* wait for training to complete */
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (running)
|
||||
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si_init_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
|
|
|
|||
|
|
@ -142,6 +142,8 @@
|
|||
#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
|
||||
#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
|
||||
|
||||
#define MC_SHARED_BLACKOUT_CNTL 0x20ac
|
||||
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
#define NOOFBANK_MASK 0x00000003
|
||||
|
|
@ -157,6 +159,20 @@
|
|||
#define NOOFGROUPS_SHIFT 12
|
||||
#define NOOFGROUPS_MASK 0x00001000
|
||||
|
||||
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
|
||||
#define TRAIN_DONE_D0 (1 << 30)
|
||||
#define TRAIN_DONE_D1 (1 << 31)
|
||||
|
||||
#define MC_SEQ_SUP_CNTL 0x28c8
|
||||
#define RUN_MASK (1 << 0)
|
||||
#define MC_SEQ_SUP_PGM 0x28cc
|
||||
|
||||
#define MC_IO_PAD_CNTL_D0 0x29d0
|
||||
#define MEM_FALL_OUT_CMD (1 << 8)
|
||||
|
||||
#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
|
||||
#define MC_SEQ_IO_DEBUG_DATA 0x2a48
|
||||
|
||||
#define HDP_HOST_PATH_CNTL 0x2C00
|
||||
#define HDP_NONSURFACE_BASE 0x2C04
|
||||
#define HDP_NONSURFACE_INFO 0x2C08
|
||||
|
|
|
|||
Loading…
Reference in a new issue