Merge branch 'drm-intel-fixes' into drm-intel-next
This commit is contained in:
commit
8b3016c4f4
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@ -1350,17 +1350,25 @@ void i915_hangcheck_elapsed(unsigned long data)
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i915_seqno_passed(i915_get_gem_seqno(dev,
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&dev_priv->render_ring),
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i915_get_tail_request(dev)->seqno)) {
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bool missed_wakeup = false;
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dev_priv->hangcheck_count = 0;
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/* Issue a wake-up to catch stuck h/w. */
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if (dev_priv->render_ring.waiting_gem_seqno |
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dev_priv->bsd_ring.waiting_gem_seqno) {
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DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
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if (dev_priv->render_ring.waiting_gem_seqno)
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DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
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if (dev_priv->bsd_ring.waiting_gem_seqno)
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DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
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if (dev_priv->render_ring.waiting_gem_seqno &&
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waitqueue_active(&dev_priv->render_ring.irq_queue)) {
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DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
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missed_wakeup = true;
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}
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if (dev_priv->bsd_ring.waiting_gem_seqno &&
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waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
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DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
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missed_wakeup = true;
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}
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if (missed_wakeup)
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DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
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return;
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}
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@ -2215,9 +2215,17 @@
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#define WM1_LP_SR_EN (1<<31)
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#define WM1_LP_LATENCY_SHIFT 24
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#define WM1_LP_LATENCY_MASK (0x7f<<24)
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#define WM1_LP_FBC_LP1_MASK (0xf<<20)
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#define WM1_LP_FBC_LP1_SHIFT 20
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#define WM1_LP_SR_MASK (0x1ff<<8)
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#define WM1_LP_SR_SHIFT 8
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#define WM1_LP_CURSOR_MASK (0x3f)
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#define WM2_LP_ILK 0x4510c
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#define WM2_LP_EN (1<<31)
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#define WM3_LP_ILK 0x45110
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#define WM3_LP_EN (1<<31)
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#define WM1S_LP_ILK 0x45120
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#define WM1S_LP_EN (1<<31)
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/* Memory latency timer register */
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#define MLTR_ILK 0x11222
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@ -3516,8 +3516,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
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reg_value = I915_READ(WM1_LP_ILK);
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reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
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WM1_LP_CURSOR_MASK);
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reg_value |= WM1_LP_SR_EN |
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(ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
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reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
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(sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
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I915_WRITE(WM1_LP_ILK, reg_value);
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@ -5839,6 +5838,9 @@ void intel_init_clock_gating(struct drm_device *dev)
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I915_WRITE(DISP_ARB_CTL,
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(I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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}
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/*
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* Based on the document from hardware guys the following bits
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