cxgb4: Add HMA support
HMA(Host Memory Access) maps a part of host memory for T6-SO memfree cards. This commit does the following: - Query FW to check if we have HMA support. If yes, the params will return HMA size configured in FW. We will dma map memory based on this size. - Also contains changes to get HMA memory information via debugfs. Signed-off-by: Arjun Vynipadath <arjun@chelsio.com> Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Michael Werner <werner@chelsio.com> Signed-off-by: Ganesh GR <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arjun Vynipadath
David S. Miller
parent
74b8da705c
commit
8b4e6b3ca2
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@ -831,6 +831,16 @@ struct vf_info {
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u16 vlan;
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};
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enum {
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HMA_DMA_MAPPED_FLAG = 1
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};
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struct hma_data {
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unsigned char flags;
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struct sg_table *sgt;
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dma_addr_t *phy_addr; /* physical address of the page */
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};
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struct mbox_list {
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struct list_head list;
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};
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@ -946,6 +956,9 @@ struct adapter {
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/* Ethtool Dump */
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struct ethtool_dump eth_dump;
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/* HMA */
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struct hma_data hma;
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};
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/* Support for "sched-class" command to allow a TX Scheduling Class to be
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@ -2617,7 +2617,7 @@ int mem_open(struct inode *inode, struct file *file)
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file->private_data = inode->i_private;
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mem = (uintptr_t)file->private_data & 0x3;
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mem = (uintptr_t)file->private_data & 0x7;
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adap = file->private_data - mem;
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(void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH);
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@ -2630,7 +2630,7 @@ static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
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{
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loff_t pos = *ppos;
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loff_t avail = file_inode(file)->i_size;
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unsigned int mem = (uintptr_t)file->private_data & 3;
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unsigned int mem = (uintptr_t)file->private_data & 0x7;
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struct adapter *adap = file->private_data - mem;
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__be32 *data;
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int ret;
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@ -3042,6 +3042,12 @@ int t4_setup_debugfs(struct adapter *adap)
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add_debugfs_mem(adap, "mc", MEM_MC,
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EXT_MEM_SIZE_G(size));
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}
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if (i & HMA_MUX_F) {
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size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
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add_debugfs_mem(adap, "hma", MEM_HMA,
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EXT_MEM1_SIZE_G(size));
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}
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}
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de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,
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@ -1736,10 +1736,11 @@ EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
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int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
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{
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struct adapter *adap;
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u32 offset, memtype, memaddr;
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u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
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u32 edc0_end, edc1_end, mc0_end, mc1_end;
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u32 offset, memtype, memaddr;
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struct adapter *adap;
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u32 hma_size = 0;
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int ret;
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adap = netdev2adap(dev);
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@ -1759,6 +1760,10 @@ int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
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size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
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mc0_size = EXT_MEM0_SIZE_G(size) << 20;
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if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
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size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
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hma_size = EXT_MEM1_SIZE_G(size) << 20;
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}
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edc0_end = edc0_size;
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edc1_end = edc0_end + edc1_size;
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mc0_end = edc1_end + mc0_size;
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@ -1770,7 +1775,10 @@ int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
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memtype = MEM_EDC1;
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memaddr = offset - edc0_end;
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} else {
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if (offset < mc0_end) {
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if (hma_size && (offset < (edc1_end + hma_size))) {
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memtype = MEM_HMA;
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memaddr = offset - edc1_end;
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} else if (offset < mc0_end) {
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memtype = MEM_MC0;
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memaddr = offset - edc1_end;
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} else if (is_t5(adap->params.chip)) {
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@ -3301,6 +3309,206 @@ static void setup_memwin_rdma(struct adapter *adap)
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}
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}
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/* HMA Definitions */
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/* The maximum number of address that can be send in a single FW cmd */
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#define HMA_MAX_ADDR_IN_CMD 5
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#define HMA_PAGE_SIZE PAGE_SIZE
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#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
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#define HMA_PAGE_ORDER \
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((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
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ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
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/* The minimum and maximum possible HMA sizes that can be specified in the FW
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* configuration(in units of MB).
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*/
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#define HMA_MIN_TOTAL_SIZE 1
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#define HMA_MAX_TOTAL_SIZE \
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(((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
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HMA_MAX_NO_FW_ADDRESS) >> 20)
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static void adap_free_hma_mem(struct adapter *adapter)
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{
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struct scatterlist *iter;
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struct page *page;
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int i;
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if (!adapter->hma.sgt)
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return;
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if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
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dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
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adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
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adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
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}
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for_each_sg(adapter->hma.sgt->sgl, iter,
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adapter->hma.sgt->orig_nents, i) {
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page = sg_page(iter);
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if (page)
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__free_pages(page, HMA_PAGE_ORDER);
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}
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kfree(adapter->hma.phy_addr);
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sg_free_table(adapter->hma.sgt);
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kfree(adapter->hma.sgt);
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adapter->hma.sgt = NULL;
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}
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static int adap_config_hma(struct adapter *adapter)
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{
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struct scatterlist *sgl, *iter;
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struct sg_table *sgt;
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struct page *newpage;
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unsigned int i, j, k;
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u32 param, hma_size;
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unsigned int ncmds;
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size_t page_size;
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u32 page_order;
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int node, ret;
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/* HMA is supported only for T6+ cards.
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* Avoid initializing HMA in kdump kernels.
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*/
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if (is_kdump_kernel() ||
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CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
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return 0;
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/* Get the HMA region size required by fw */
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param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
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FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
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ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
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1, ¶m, &hma_size);
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/* An error means card has its own memory or HMA is not supported by
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* the firmware. Return without any errors.
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*/
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if (ret || !hma_size)
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return 0;
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if (hma_size < HMA_MIN_TOTAL_SIZE ||
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hma_size > HMA_MAX_TOTAL_SIZE) {
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dev_err(adapter->pdev_dev,
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"HMA size %uMB beyond bounds(%u-%lu)MB\n",
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hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
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return -EINVAL;
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}
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page_size = HMA_PAGE_SIZE;
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page_order = HMA_PAGE_ORDER;
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adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
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if (unlikely(!adapter->hma.sgt)) {
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dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
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return -ENOMEM;
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}
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sgt = adapter->hma.sgt;
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/* FW returned value will be in MB's
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*/
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sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
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if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
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dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
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kfree(adapter->hma.sgt);
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adapter->hma.sgt = NULL;
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return -ENOMEM;
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}
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sgl = adapter->hma.sgt->sgl;
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node = dev_to_node(adapter->pdev_dev);
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for_each_sg(sgl, iter, sgt->orig_nents, i) {
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newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL,
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page_order);
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if (!newpage) {
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dev_err(adapter->pdev_dev,
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"Not enough memory for HMA page allocation\n");
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ret = -ENOMEM;
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goto free_hma;
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}
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sg_set_page(iter, newpage, page_size << page_order, 0);
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}
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sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
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DMA_BIDIRECTIONAL);
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if (!sgt->nents) {
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dev_err(adapter->pdev_dev,
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"Not enough memory for HMA DMA mapping");
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ret = -ENOMEM;
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goto free_hma;
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}
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adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
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adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
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GFP_KERNEL);
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if (unlikely(!adapter->hma.phy_addr))
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goto free_hma;
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for_each_sg(sgl, iter, sgt->nents, i) {
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newpage = sg_page(iter);
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adapter->hma.phy_addr[i] = sg_dma_address(iter);
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}
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ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
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/* Pass on the addresses to firmware */
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for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
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struct fw_hma_cmd hma_cmd;
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u8 naddr = HMA_MAX_ADDR_IN_CMD;
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u8 soc = 0, eoc = 0;
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u8 hma_mode = 1; /* Presently we support only Page table mode */
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soc = (i == 0) ? 1 : 0;
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eoc = (i == ncmds - 1) ? 1 : 0;
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/* For last cmd, set naddr corresponding to remaining
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* addresses
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*/
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if (i == ncmds - 1) {
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naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
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naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
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}
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memset(&hma_cmd, 0, sizeof(hma_cmd));
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hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
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FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
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hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
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hma_cmd.mode_to_pcie_params =
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htonl(FW_HMA_CMD_MODE_V(hma_mode) |
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FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
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/* HMA cmd size specified in MB's */
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hma_cmd.naddr_size =
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htonl(FW_HMA_CMD_SIZE_V(hma_size) |
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FW_HMA_CMD_NADDR_V(naddr));
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/* Total Page size specified in units of 4K */
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hma_cmd.addr_size_pkd =
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htonl(FW_HMA_CMD_ADDR_SIZE_V
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((page_size << page_order) >> 12));
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/* Fill the 5 addresses */
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for (j = 0; j < naddr; j++) {
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hma_cmd.phy_address[j] =
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cpu_to_be64(adapter->hma.phy_addr[j + k]);
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}
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ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
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sizeof(hma_cmd), &hma_cmd);
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if (ret) {
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dev_err(adapter->pdev_dev,
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"HMA FW command failed with err %d\n", ret);
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goto free_hma;
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}
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}
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if (!ret)
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dev_info(adapter->pdev_dev,
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"Reserved %uMB host memory for HMA\n", hma_size);
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return ret;
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free_hma:
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adap_free_hma_mem(adapter);
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return ret;
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}
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static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
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{
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u32 v;
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@ -3754,6 +3962,12 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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if (ret < 0)
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goto bye;
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/* We will proceed even if HMA init fails. */
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ret = adap_config_hma(adapter);
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if (ret)
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dev_err(adapter->pdev_dev,
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"HMA configuration failed with error %d\n", ret);
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/*
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* And finally tell the firmware to initialize itself using the
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* parameters from the Configuration File.
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@ -3960,6 +4174,11 @@ static int adap_init0(struct adapter *adap)
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* effect. Otherwise, it's time to try initializing the adapter.
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*/
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if (state == DEV_STATE_INIT) {
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ret = adap_config_hma(adap);
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if (ret)
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dev_err(adap->pdev_dev,
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"HMA configuration failed with error %d\n",
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ret);
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dev_info(adap->pdev_dev, "Coming up as %s: "\
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"Adapter already initialized\n",
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adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
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@ -4349,6 +4568,7 @@ static int adap_init0(struct adapter *adap)
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* happened to HW/FW, stop issuing commands.
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*/
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bye:
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adap_free_hma_mem(adap);
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kfree(adap->sge.egr_map);
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kfree(adap->sge.ingr_map);
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kfree(adap->sge.starving_fl);
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@ -5576,6 +5796,8 @@ static void remove_one(struct pci_dev *pdev)
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t4_uld_clean_up(adapter);
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}
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adap_free_hma_mem(adapter);
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disable_interrupts(adapter);
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for_each_port(adapter, i)
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@ -487,7 +487,7 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
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* t4_memory_rw_init - Get memory window relative offset, base, and size.
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* @adap: the adapter
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* @win: PCI-E Memory Window to use
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* @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
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* @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
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* @mem_off: memory relative offset with respect to @mtype.
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* @mem_base: configured memory base address.
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* @mem_aperture: configured memory window aperture.
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@ -766,6 +766,7 @@ enum fw_cmd_opcodes {
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FW_DEVLOG_CMD = 0x25,
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FW_CLIP_CMD = 0x28,
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FW_PTP_CMD = 0x3e,
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FW_HMA_CMD = 0x3f,
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FW_LASTC2E_CMD = 0x40,
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FW_ERROR_CMD = 0x80,
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FW_DEBUG_CMD = 0x81,
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@ -1132,6 +1133,7 @@ enum fw_memtype_cf {
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FW_MEMTYPE_CF_FLASH = 0x4,
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FW_MEMTYPE_CF_INTERNAL = 0x5,
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FW_MEMTYPE_CF_EXTMEM1 = 0x6,
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FW_MEMTYPE_CF_HMA = 0x7,
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};
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struct fw_caps_config_cmd {
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@ -1210,6 +1212,7 @@ enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
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FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
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FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
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FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
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};
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/*
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@ -3435,6 +3438,59 @@ struct fw_debug_cmd {
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#define FW_DEBUG_CMD_TYPE_G(x) \
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(((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
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struct fw_hma_cmd {
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__be32 op_pkd;
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__be32 retval_len16;
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__be32 mode_to_pcie_params;
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__be32 naddr_size;
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__be32 addr_size_pkd;
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__be32 r6;
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__be64 phy_address[5];
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};
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#define FW_HMA_CMD_MODE_S 31
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#define FW_HMA_CMD_MODE_M 0x1
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#define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S)
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#define FW_HMA_CMD_MODE_G(x) \
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(((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
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#define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U)
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#define FW_HMA_CMD_SOC_S 30
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#define FW_HMA_CMD_SOC_M 0x1
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#define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S)
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#define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
|
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#define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U)
|
||||
|
||||
#define FW_HMA_CMD_EOC_S 29
|
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#define FW_HMA_CMD_EOC_M 0x1
|
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#define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S)
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||||
#define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
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#define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U)
|
||||
|
||||
#define FW_HMA_CMD_PCIE_PARAMS_S 0
|
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#define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff
|
||||
#define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
|
||||
#define FW_HMA_CMD_PCIE_PARAMS_G(x) \
|
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(((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
|
||||
|
||||
#define FW_HMA_CMD_NADDR_S 12
|
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#define FW_HMA_CMD_NADDR_M 0x3f
|
||||
#define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S)
|
||||
#define FW_HMA_CMD_NADDR_G(x) \
|
||||
(((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
|
||||
|
||||
#define FW_HMA_CMD_SIZE_S 0
|
||||
#define FW_HMA_CMD_SIZE_M 0xfff
|
||||
#define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S)
|
||||
#define FW_HMA_CMD_SIZE_G(x) \
|
||||
(((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
|
||||
|
||||
#define FW_HMA_CMD_ADDR_SIZE_S 11
|
||||
#define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff
|
||||
#define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S)
|
||||
#define FW_HMA_CMD_ADDR_SIZE_G(x) \
|
||||
(((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
|
||||
|
||||
enum pcie_fw_eval {
|
||||
PCIE_FW_EVAL_CRASH = 0,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue