ASoC: stm32: i2s: fix IRQ clearing
Because of regmap cache, interrupts may not be cleared as expected. Declare IFCR register as write only and make writings to IFCR register unconditional. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
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ae3f563a85
commit
8ba3c5215d
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@ -247,8 +247,8 @@ static irqreturn_t stm32_i2s_isr(int irq, void *devid)
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return IRQ_NONE;
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return IRQ_NONE;
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}
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}
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regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, flags);
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I2S_IFCR_MASK, flags);
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if (flags & I2S_SR_OVR) {
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if (flags & I2S_SR_OVR) {
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dev_dbg(&pdev->dev, "Overrun\n");
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dev_dbg(&pdev->dev, "Overrun\n");
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@ -277,7 +277,6 @@ static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
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case STM32_I2S_CFG2_REG:
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case STM32_I2S_CFG2_REG:
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case STM32_I2S_IER_REG:
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case STM32_I2S_IER_REG:
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case STM32_I2S_SR_REG:
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case STM32_I2S_SR_REG:
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case STM32_I2S_IFCR_REG:
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case STM32_I2S_TXDR_REG:
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case STM32_I2S_TXDR_REG:
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case STM32_I2S_RXDR_REG:
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case STM32_I2S_RXDR_REG:
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case STM32_I2S_CGFR_REG:
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case STM32_I2S_CGFR_REG:
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@ -559,8 +558,8 @@ static int stm32_i2s_startup(struct snd_pcm_substream *substream,
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i2s->refcount++;
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i2s->refcount++;
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spin_unlock(&i2s->lock_fd);
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spin_unlock(&i2s->lock_fd);
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return regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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}
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}
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static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
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static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
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@ -611,8 +610,8 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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return ret;
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return ret;
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}
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}
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regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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I2S_IFCR_MASK, I2S_IFCR_MASK);
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if (playback_flg) {
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if (playback_flg) {
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ier = I2S_IER_UDRIE;
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ier = I2S_IER_UDRIE;
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