[Blackfin] arch: Enable both edge triggered GPIO IRQs on BF54x and use irq_to_gpio()
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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@ -483,6 +483,10 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
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static unsigned char irq2pint_lut[NR_PINTS];
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static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
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static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
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static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
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struct pin_int_t {
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unsigned int mask_set;
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unsigned int mask_clear;
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@ -549,13 +553,20 @@ void init_pint_lut(void)
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}
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static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
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static void bfin_gpio_ack_irq(unsigned int irq)
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{
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u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
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u32 pintbit = PINT_BIT(pint_val);
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u8 bank = PINT_2_BANK(pint_val);
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if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
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if (pint[bank]->invert_set & pintbit)
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pint[bank]->invert_clear = pintbit;
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else
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pint[bank]->invert_set = pintbit;
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}
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pint[bank]->request = pintbit;
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pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
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SSYNC();
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}
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@ -565,6 +576,13 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
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u32 pintbit = PINT_BIT(pint_val);
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u8 bank = PINT_2_BANK(pint_val);
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if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
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if (pint[bank]->invert_set & pintbit)
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pint[bank]->invert_clear = pintbit;
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else
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pint[bank]->invert_set = pintbit;
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}
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pint[bank]->request = pintbit;
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pint[bank]->mask_clear = pintbit;
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SSYNC();
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@ -593,7 +611,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
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{
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unsigned int ret;
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char buf[8];
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u16 gpionr = irq - IRQ_PA0;
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u16 gpionr = irq_to_gpio(irq);
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u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
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if (pint_val == IRQ_NOT_AVAIL) {
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@ -618,9 +636,11 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
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static void bfin_gpio_irq_shutdown(unsigned int irq)
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{
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u16 gpionr = irq_to_gpio(irq);
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bfin_gpio_mask_irq(irq);
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gpio_free(irq - IRQ_PA0);
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gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
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gpio_free(gpionr);
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gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
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}
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static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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@ -628,7 +648,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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unsigned int ret;
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char buf[8];
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u16 gpionr = irq - IRQ_PA0;
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u16 gpionr = irq_to_gpio(irq);
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u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
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u32 pintbit = PINT_BIT(pint_val);
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u8 bank = PINT_2_BANK(pint_val);
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@ -660,29 +680,34 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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gpio_direction_input(gpionr);
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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pint[bank]->edge_set = pintbit;
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} else {
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pint[bank]->edge_clear = pintbit;
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}
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if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
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pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
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else
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pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
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pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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pint[bank]->invert_set = pintbit;
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else
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pint[bank]->invert_set = pintbit;
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if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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gpio_both_edge_triggered[bank] |= pintbit;
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if (gpio_get_value(gpionr))
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pint[bank]->invert_set = pintbit;
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else
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pint[bank]->invert_clear = pintbit;
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} else {
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gpio_both_edge_triggered[bank] &= ~pintbit;
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}
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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pint[bank]->edge_set = pintbit;
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set_irq_handler(irq, handle_edge_irq);
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} else {
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pint[bank]->edge_clear = pintbit;
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set_irq_handler(irq, handle_level_irq);
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}
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SSYNC();
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
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set_irq_handler(irq, handle_edge_irq);
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else
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set_irq_handler(irq, handle_level_irq);
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return 0;
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}
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