irqchip: ingenic: Alloc generic chips from IRQ domain
By creating the generic chips from the IRQ domain, we don't rely on the JZ4740_IRQ_BASE macro. It also makes the code a bit cleaner. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1570015525-27018-5-git-send-email-zhouyanjie@zoho.com
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@ -36,12 +36,14 @@ static irqreturn_t intc_cascade(int irq, void *data)
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{
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struct ingenic_intc_data *intc = irq_get_handler_data(irq);
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struct irq_domain *domain = intc->domain;
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struct irq_chip_generic *gc;
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uint32_t irq_reg;
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unsigned i;
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for (i = 0; i < intc->num_chips; i++) {
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irq_reg = readl(intc->base + (i * CHIP_SIZE) +
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JZ_REG_INTC_PENDING);
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gc = irq_get_domain_generic_chip(domain, i * 32);
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irq_reg = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
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if (!irq_reg)
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continue;
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@ -92,7 +94,7 @@ static int __init ingenic_intc_of_init(struct device_node *node,
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domain = irq_domain_add_legacy(node, num_chips * 32,
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JZ4740_IRQ_BASE, 0,
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&irq_domain_simple_ops, NULL);
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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err = -ENOMEM;
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goto out_unmap_base;
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@ -100,17 +102,17 @@ static int __init ingenic_intc_of_init(struct device_node *node,
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intc->domain = domain;
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for (i = 0; i < num_chips; i++) {
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/* Mask all irqs */
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writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
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JZ_REG_INTC_SET_MASK);
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err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
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handle_level_irq, 0,
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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if (err)
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goto out_domain_remove;
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gc = irq_alloc_generic_chip("INTC", 1,
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JZ4740_IRQ_BASE + (i * 32),
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intc->base + (i * CHIP_SIZE),
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handle_level_irq);
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for (i = 0; i < num_chips; i++) {
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gc = irq_get_domain_generic_chip(domain, i * 32);
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gc->wake_enabled = IRQ_MSK(32);
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gc->reg_base = intc->base + (i * CHIP_SIZE);
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ct = gc->chip_types;
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ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
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@ -121,13 +123,15 @@ static int __init ingenic_intc_of_init(struct device_node *node,
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0,
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IRQ_NOPROBE | IRQ_LEVEL);
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/* Mask all irqs */
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irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
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}
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setup_irq(parent_irq, &intc_cascade_action);
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return 0;
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out_domain_remove:
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irq_domain_remove(domain);
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out_unmap_base:
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iounmap(intc->base);
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out_unmap_irq:
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