pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC
This adds the initial support of the Broadcom NSP gpio-a driver. Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Yendapally Reddy Dhananjaya Reddy
Linus Walleij
parent
bb37baeaaf
commit
8bfcbbbcab
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@ -54,3 +54,20 @@ config PINCTRL_CYGNUS_MUX
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The Broadcom Cygnus IOMUX driver supports group based IOMUX
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configuration, with the exception that certain individual pins
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can be overrided to GPIO function
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config PINCTRL_NSP_GPIO
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bool "Broadcom NSP GPIO (with PINCONF) driver"
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depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
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select GPIOLIB_IRQCHIP
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select PINCONF
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select GENERIC_PINCONF
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default ARCH_BCM_NSP
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help
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Say yes here to enable the Broadcom NSP GPIO driver.
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The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
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supported by this driver.
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The ChipcommonA GPIO controller support basic PINCONF functions such
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as bias pull up, pull down, and drive strength configurations, when
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these pins are muxed to GPIO.
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@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
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obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
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obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o
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obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
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obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o
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@ -0,0 +1,749 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
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* supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
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* pull up/down, slew and drive strength are also supported in this driver.
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*
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* Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
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* through the interaction with the NSP IOMUX controller.
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*/
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/slab.h>
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#include "../pinctrl-utils.h"
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#define NSP_CHIP_A_INT_STATUS 0x00
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#define NSP_CHIP_A_INT_MASK 0x04
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#define NSP_GPIO_DATA_IN 0x40
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#define NSP_GPIO_DATA_OUT 0x44
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#define NSP_GPIO_OUT_EN 0x48
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#define NSP_GPIO_INT_POLARITY 0x50
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#define NSP_GPIO_INT_MASK 0x54
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#define NSP_GPIO_EVENT 0x58
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#define NSP_GPIO_EVENT_INT_MASK 0x5c
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#define NSP_GPIO_EVENT_INT_POLARITY 0x64
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#define NSP_CHIP_A_GPIO_INT_BIT 0x01
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/* I/O parameters offset for chipcommon A GPIO */
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#define NSP_GPIO_DRV_CTRL 0x00
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#define NSP_GPIO_HYSTERESIS_EN 0x10
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#define NSP_GPIO_SLEW_RATE_EN 0x14
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#define NSP_PULL_UP_EN 0x18
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#define NSP_PULL_DOWN_EN 0x1c
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#define GPIO_DRV_STRENGTH_BITS 0x03
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/*
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* nsp GPIO core
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*
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* @dev: pointer to device
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* @base: I/O register base for nsp GPIO controller
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* @io_ctrl: I/O register base for PINCONF support outside the GPIO block
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* @gc: GPIO chip
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* @pctl: pointer to pinctrl_dev
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* @pctldesc: pinctrl descriptor
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* @irq_domain: pointer to irq domain
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* @lock: lock to protect access to I/O registers
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*/
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struct nsp_gpio {
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struct device *dev;
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void __iomem *base;
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void __iomem *io_ctrl;
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struct gpio_chip gc;
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struct pinctrl_dev *pctl;
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struct pinctrl_desc pctldesc;
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struct irq_domain *irq_domain;
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spinlock_t lock;
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};
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enum base_type {
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REG,
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IO_CTRL
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};
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static inline struct nsp_gpio *to_nsp_gpio(struct gpio_chip *gc)
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{
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return container_of(gc, struct nsp_gpio, gc);
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}
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/*
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* Mapping from PINCONF pins to GPIO pins is 1-to-1
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*/
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static inline unsigned nsp_pin_to_gpio(unsigned pin)
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{
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return pin;
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}
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/*
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* nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
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* nsp GPIO register
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*
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* @nsp_gpio: nsp GPIO device
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* @base_type: reg base to modify
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* @reg: register offset
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* @gpio: GPIO pin
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* @set: set or clear
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*/
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static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
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unsigned int reg, unsigned gpio, bool set)
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{
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u32 val;
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void __iomem *base_address;
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if (address == IO_CTRL)
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base_address = chip->io_ctrl;
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else
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base_address = chip->base;
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val = readl(base_address + reg);
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if (set)
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val |= BIT(gpio);
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else
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val &= ~BIT(gpio);
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writel(val, base_address + reg);
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}
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/*
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* nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
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* nsp GPIO register
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*/
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static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
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unsigned int reg, unsigned gpio)
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{
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if (address == IO_CTRL)
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return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
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else
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return !!(readl(chip->base + reg) & BIT(gpio));
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}
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static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
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{
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struct nsp_gpio *chip = (struct nsp_gpio *)data;
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struct gpio_chip gc = chip->gc;
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int bit;
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unsigned long int_bits = 0;
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u32 int_status;
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/* go through the entire GPIOs and handle all interrupts */
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int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
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if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
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unsigned int event, level;
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/* Get level and edge interrupts */
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event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
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readl(chip->base + NSP_GPIO_EVENT);
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level = readl(chip->base + NSP_GPIO_DATA_IN) ^
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readl(chip->base + NSP_GPIO_INT_POLARITY);
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level &= readl(chip->base + NSP_GPIO_INT_MASK);
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int_bits = level | event;
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for_each_set_bit(bit, &int_bits, gc.ngpio) {
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/*
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* Clear the interrupt before invoking the
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* handler, so we do not leave any window
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*/
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writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
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generic_handle_irq(
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irq_linear_revmap(chip->irq_domain, bit));
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}
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}
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return int_bits ? IRQ_HANDLED : IRQ_NONE;
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}
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static void nsp_gpio_irq_ack(struct irq_data *d)
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{
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned gpio = d->hwirq;
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u32 val = BIT(gpio);
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u32 trigger_type;
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trigger_type = irq_get_trigger_type(d->irq);
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if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
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}
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/*
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* nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
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*
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* @d: IRQ chip data
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* @unmask: mask/unmask GPIO interrupt
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*/
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static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
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{
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned gpio = d->hwirq;
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u32 trigger_type;
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trigger_type = irq_get_trigger_type(d->irq);
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if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
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else
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nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
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}
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static void nsp_gpio_irq_mask(struct irq_data *d)
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{
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static void nsp_gpio_irq_unmask(struct irq_data *d)
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{
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_gpio_irq_set_mask(d, true);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
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unsigned gpio = d->hwirq;
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bool level_low;
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bool falling;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
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level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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falling = false;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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falling = true;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level_low = false;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level_low = true;
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break;
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default:
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dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
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type);
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spin_unlock_irqrestore(&chip->lock, flags);
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return -EINVAL;
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}
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nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
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nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
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level_low ? "true" : "false", falling ? "true" : "false");
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return 0;
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}
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static struct irq_chip nsp_gpio_irq_chip = {
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.name = "gpio-a",
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.irq_enable = nsp_gpio_irq_unmask,
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.irq_disable = nsp_gpio_irq_mask,
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.irq_ack = nsp_gpio_irq_ack,
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.irq_mask = nsp_gpio_irq_mask,
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.irq_unmask = nsp_gpio_irq_unmask,
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.irq_set_type = nsp_gpio_irq_set_type,
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};
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/*
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* Request the nsp IOMUX pinmux controller to mux individual pins to GPIO
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*/
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static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
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{
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unsigned gpio = gc->base + offset;
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return pinctrl_request_gpio(gpio);
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}
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static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
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{
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unsigned gpio = gc->base + offset;
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pinctrl_free_gpio(gpio);
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}
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static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
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{
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struct nsp_gpio *chip = to_nsp_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
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return 0;
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}
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static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
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int val)
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{
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struct nsp_gpio *chip = to_nsp_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
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return 0;
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}
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static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
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{
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struct nsp_gpio *chip = to_nsp_gpio(gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
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}
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static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
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{
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struct nsp_gpio *chip = to_nsp_gpio(gc);
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return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
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}
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static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct nsp_gpio *chip = to_nsp_gpio(gc);
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return irq_linear_revmap(chip->irq_domain, offset);
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}
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static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 1;
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}
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/*
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* Only one group: "gpio_grp", since this local pinctrl device only performs
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* GPIO specific PINCONF configurations
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*/
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static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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return "gpio_grp";
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}
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static const struct pinctrl_ops nsp_pctrl_ops = {
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.get_groups_count = nsp_get_groups_count,
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.get_group_name = nsp_get_group_name,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u16 slew)
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{
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if (slew)
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nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
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else
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nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
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return 0;
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}
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static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
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bool pull_up, bool pull_down)
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
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nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
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spin_unlock_irqrestore(&chip->lock, flags);
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dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
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gpio, pull_up, pull_down);
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return 0;
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}
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static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
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bool *pull_up, bool *pull_down)
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{
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
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*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
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u16 strength)
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{
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u32 offset, shift, i;
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u32 val;
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unsigned long flags;
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/* make sure drive strength is supported */
|
||||
if (strength < 2 || strength > 16 || (strength % 2))
|
||||
return -ENOTSUPP;
|
||||
|
||||
shift = gpio;
|
||||
offset = NSP_GPIO_DRV_CTRL;
|
||||
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
|
||||
strength);
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
strength = (strength / 2) - 1;
|
||||
for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
|
||||
val = readl(chip->io_ctrl + offset);
|
||||
val &= ~BIT(shift);
|
||||
val |= ((strength >> (i-1)) & 0x1) << shift;
|
||||
writel(val, chip->io_ctrl + offset);
|
||||
offset += 4;
|
||||
}
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
|
||||
u16 *strength)
|
||||
{
|
||||
unsigned int i, offset, shift;
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
|
||||
offset = NSP_GPIO_DRV_CTRL;
|
||||
shift = gpio;
|
||||
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
*strength = 0;
|
||||
for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
|
||||
val = readl(chip->io_ctrl + offset) & BIT(shift);
|
||||
val >>= shift;
|
||||
*strength += (val << i);
|
||||
offset += 4;
|
||||
}
|
||||
|
||||
/* convert to mA */
|
||||
*strength = (*strength + 1) * 2;
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned long *config)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned long *configs, unsigned num_configs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum pin_config_param param = pinconf_to_config_param(*config);
|
||||
unsigned int gpio;
|
||||
u16 arg = 0;
|
||||
bool pull_up, pull_down;
|
||||
int ret;
|
||||
|
||||
gpio = nsp_pin_to_gpio(pin);
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
||||
if ((pull_up == false) && (pull_down == false))
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
||||
if (pull_up)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
|
||||
if (pull_down)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
ret = nsp_gpio_get_strength(chip, gpio, &arg);
|
||||
if (ret)
|
||||
return ret;
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
unsigned long *configs, unsigned num_configs)
|
||||
{
|
||||
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum pin_config_param param;
|
||||
u16 arg;
|
||||
unsigned int i, gpio;
|
||||
int ret = -ENOTSUPP;
|
||||
|
||||
gpio = nsp_pin_to_gpio(pin);
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
arg = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
ret = nsp_gpio_set_pull(chip, gpio, false, false);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
ret = nsp_gpio_set_pull(chip, gpio, true, false);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
ret = nsp_gpio_set_pull(chip, gpio, false, true);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
ret = nsp_gpio_set_strength(chip, gpio, arg);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
ret = nsp_gpio_set_slew(chip, gpio, arg);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(chip->dev, "invalid configuration\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops nsp_pconf_ops = {
|
||||
.is_generic = true,
|
||||
.pin_config_get = nsp_pin_config_get,
|
||||
.pin_config_set = nsp_pin_config_set,
|
||||
.pin_config_group_get = nsp_pin_config_group_get,
|
||||
.pin_config_group_set = nsp_pin_config_group_set,
|
||||
};
|
||||
|
||||
/*
|
||||
* NSP GPIO controller supports some PINCONF related configurations such as
|
||||
* pull up, pull down, slew and drive strength, when the pin is configured
|
||||
* to GPIO.
|
||||
*
|
||||
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
|
||||
* local GPIO pins
|
||||
*/
|
||||
static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
|
||||
{
|
||||
struct pinctrl_desc *pctldesc = &chip->pctldesc;
|
||||
struct pinctrl_pin_desc *pins;
|
||||
struct gpio_chip *gc = &chip->gc;
|
||||
int i;
|
||||
|
||||
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
|
||||
if (!pins)
|
||||
return -ENOMEM;
|
||||
for (i = 0; i < gc->ngpio; i++) {
|
||||
pins[i].number = i;
|
||||
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
|
||||
"gpio-%d", i);
|
||||
if (!pins[i].name)
|
||||
return -ENOMEM;
|
||||
}
|
||||
pctldesc->name = dev_name(chip->dev);
|
||||
pctldesc->pctlops = &nsp_pctrl_ops;
|
||||
pctldesc->pins = pins;
|
||||
pctldesc->npins = gc->ngpio;
|
||||
pctldesc->confops = &nsp_pconf_ops;
|
||||
|
||||
chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
|
||||
if (IS_ERR(chip->pctl)) {
|
||||
dev_err(chip->dev, "unable to register pinctrl device\n");
|
||||
return PTR_ERR(chip->pctl);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id nsp_gpio_of_match[] = {
|
||||
{.compatible = "brcm,nsp-gpio-a",},
|
||||
{}
|
||||
};
|
||||
|
||||
static int nsp_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
struct nsp_gpio *chip;
|
||||
struct gpio_chip *gc;
|
||||
u32 val, count;
|
||||
int irq, ret;
|
||||
|
||||
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
|
||||
dev_err(&pdev->dev, "Missing ngpios OF property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->dev = dev;
|
||||
platform_set_drvdata(pdev, chip);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
chip->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(chip->base)) {
|
||||
dev_err(dev, "unable to map I/O memory\n");
|
||||
return PTR_ERR(chip->base);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
chip->io_ctrl = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(chip->io_ctrl)) {
|
||||
dev_err(dev, "unable to map I/O memory\n");
|
||||
return PTR_ERR(chip->io_ctrl);
|
||||
}
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
gc = &chip->gc;
|
||||
gc->base = -1;
|
||||
gc->can_sleep = false;
|
||||
gc->ngpio = val;
|
||||
gc->label = dev_name(dev);
|
||||
gc->dev = dev;
|
||||
gc->of_node = dev->of_node;
|
||||
gc->request = nsp_gpio_request;
|
||||
gc->free = nsp_gpio_free;
|
||||
gc->direction_input = nsp_gpio_direction_input;
|
||||
gc->direction_output = nsp_gpio_direction_output;
|
||||
gc->set = nsp_gpio_set;
|
||||
gc->get = nsp_gpio_get;
|
||||
gc->to_irq = nsp_gpio_to_irq;
|
||||
|
||||
/* optional GPIO interrupt support */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq > 0) {
|
||||
/* Create irq domain so that each pin can be assigned an IRQ.*/
|
||||
chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
|
||||
&irq_domain_simple_ops,
|
||||
chip);
|
||||
if (!chip->irq_domain) {
|
||||
dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Map each gpio to an IRQ and set the handler for gpiolib. */
|
||||
for (count = 0; count < gc->ngpio; count++) {
|
||||
int irq = irq_create_mapping(chip->irq_domain, count);
|
||||
|
||||
irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
|
||||
handle_simple_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
irq_set_chip_data(irq, chip);
|
||||
}
|
||||
|
||||
/* Install ISR for this GPIO controller. */
|
||||
ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
|
||||
IRQF_SHARED, "gpio-a", chip);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
|
||||
irq, ret);
|
||||
goto err_rm_gpiochip;
|
||||
}
|
||||
|
||||
val = readl(chip->base + NSP_CHIP_A_INT_MASK);
|
||||
val = val | NSP_CHIP_A_GPIO_INT_BIT;
|
||||
writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
|
||||
}
|
||||
|
||||
ret = gpiochip_add(gc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "unable to add GPIO chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = nsp_gpio_register_pinconf(chip);
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to register pinconf\n");
|
||||
goto err_rm_gpiochip;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_rm_gpiochip:
|
||||
gpiochip_remove(gc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver nsp_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "nsp-gpio-a",
|
||||
.of_match_table = nsp_gpio_of_match,
|
||||
},
|
||||
.probe = nsp_gpio_probe,
|
||||
};
|
||||
|
||||
static int __init nsp_gpio_init(void)
|
||||
{
|
||||
return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe);
|
||||
}
|
||||
arch_initcall_sync(nsp_gpio_init);
|
||||
Loading…
Reference in New Issue