powerpc/eeh: I/O chip EEH state retrieval
The patch adds I/O chip backend to retrieve the state for the indicated PE. While the PE state is temperarily unavailable, the upper layer (powernv platform) should return default delay (1 second). Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -116,10 +116,107 @@ static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
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return ret;
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}
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/**
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* ioda_eeh_get_state - Retrieve the state of PE
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* @pe: EEH PE
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*
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* The PE's state should be retrieved from the PEEV, PEST
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* IODA tables. Since the OPAL has exported the function
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* to do it, it'd better to use that.
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*/
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static int ioda_eeh_get_state(struct eeh_pe *pe)
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{
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s64 ret = 0;
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u8 fstate;
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u16 pcierr;
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u32 pe_no;
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int result;
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struct pci_controller *hose = pe->phb;
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struct pnv_phb *phb = hose->private_data;
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/*
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* Sanity check on PE address. The PHB PE address should
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* be zero.
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*/
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if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
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pr_err("%s: PE address %x out of range [0, %x] "
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"on PHB#%x\n",
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__func__, pe->addr, phb->ioda.total_pe,
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hose->global_number);
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return EEH_STATE_NOT_SUPPORT;
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}
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/* Retrieve PE status through OPAL */
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pe_no = pe->addr;
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ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
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&fstate, &pcierr, NULL);
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if (ret) {
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pr_err("%s: Failed to get EEH status on "
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"PHB#%x-PE#%x\n, err=%lld\n",
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__func__, hose->global_number, pe_no, ret);
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return EEH_STATE_NOT_SUPPORT;
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}
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/* Check PHB status */
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if (pe->type & EEH_PE_PHB) {
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result = 0;
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result &= ~EEH_STATE_RESET_ACTIVE;
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if (pcierr != OPAL_EEH_PHB_ERROR) {
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result |= EEH_STATE_MMIO_ACTIVE;
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result |= EEH_STATE_DMA_ACTIVE;
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result |= EEH_STATE_MMIO_ENABLED;
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result |= EEH_STATE_DMA_ENABLED;
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}
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return result;
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}
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/* Parse result out */
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result = 0;
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switch (fstate) {
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case OPAL_EEH_STOPPED_NOT_FROZEN:
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result &= ~EEH_STATE_RESET_ACTIVE;
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result |= EEH_STATE_MMIO_ACTIVE;
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result |= EEH_STATE_DMA_ACTIVE;
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result |= EEH_STATE_MMIO_ENABLED;
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result |= EEH_STATE_DMA_ENABLED;
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break;
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case OPAL_EEH_STOPPED_MMIO_FREEZE:
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result &= ~EEH_STATE_RESET_ACTIVE;
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result |= EEH_STATE_DMA_ACTIVE;
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result |= EEH_STATE_DMA_ENABLED;
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break;
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case OPAL_EEH_STOPPED_DMA_FREEZE:
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result &= ~EEH_STATE_RESET_ACTIVE;
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result |= EEH_STATE_MMIO_ACTIVE;
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result |= EEH_STATE_MMIO_ENABLED;
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break;
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case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
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result &= ~EEH_STATE_RESET_ACTIVE;
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break;
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case OPAL_EEH_STOPPED_RESET:
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result |= EEH_STATE_RESET_ACTIVE;
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break;
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case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
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result |= EEH_STATE_UNAVAILABLE;
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break;
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case OPAL_EEH_STOPPED_PERM_UNAVAIL:
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result |= EEH_STATE_NOT_SUPPORT;
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break;
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default:
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pr_warning("%s: Unexpected EEH status 0x%x "
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"on PHB#%x-PE#%x\n",
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__func__, fstate, hose->global_number, pe_no);
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}
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return result;
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}
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struct pnv_eeh_ops ioda_eeh_ops = {
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.post_init = ioda_eeh_post_init,
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.set_option = ioda_eeh_set_option,
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.get_state = NULL,
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.get_state = ioda_eeh_get_state,
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.reset = NULL,
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.get_log = NULL,
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.configure_bridge = NULL,
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