mtd: spi-nor: introduce SR_BP_SHIFT define
The shift variable of SR_BP is conclusive because the first bit of SR_BP is fixed on all known flashes. Replace ffs operation with SR_BP_SHIFT. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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@ -1767,7 +1767,6 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
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struct mtd_info *mtd = &nor->mtd;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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u8 tb_mask = SR_TB_BIT5;
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int shift = ffs(mask) - 1;
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int pow;
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if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
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@ -1778,7 +1777,7 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
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*ofs = 0;
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*len = 0;
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} else {
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pow = ((sr & mask) ^ mask) >> shift;
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pow = ((sr & mask) ^ mask) >> SR_BP_SHIFT;
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*len = mtd->size >> pow;
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if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
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*ofs = 0;
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@ -1860,7 +1859,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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int ret, status_old, status_new;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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u8 tb_mask = SR_TB_BIT5;
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u8 shift = ffs(mask) - 1, pow, val;
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u8 pow, val;
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loff_t lock_len;
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bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
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bool use_top;
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@ -1909,7 +1908,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
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*/
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pow = ilog2(mtd->size) - ilog2(lock_len);
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val = mask - (pow << shift);
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val = mask - (pow << SR_BP_SHIFT);
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if (val & ~mask)
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return -EINVAL;
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/* Don't "lock" with no region! */
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@ -1946,7 +1945,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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int ret, status_old, status_new;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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u8 tb_mask = SR_TB_BIT5;
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u8 shift = ffs(mask) - 1, pow, val;
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u8 pow, val;
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loff_t lock_len;
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bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
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bool use_top;
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@ -1997,7 +1996,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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if (lock_len == 0) {
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val = 0; /* fully unlocked */
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} else {
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val = mask - (pow << shift);
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val = mask - (pow << SR_BP_SHIFT);
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/* Some power-of-two sizes are not supported */
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if (val & ~mask)
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return -EINVAL;
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@ -137,6 +137,8 @@
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#define SR1_QUAD_EN_BIT6 BIT(6)
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#define SR_BP_SHIFT 2
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/* Enhanced Volatile Configuration Register bits */
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#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
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