drm/radeon: add gpu init support for CIK (v9)
v2: tiling fixes v3: more tiling fixes v4: more tiling fixes v5: additional register init v6: rebase v7: fix gb_addr_config for KV/KB v8: drop wip KV bits for now, add missing config reg v9: fix cu count on Bonaire Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
efad86db4e
commit
8cc1a5328b
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@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
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evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
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atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
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si_blit_shaders.o radeon_prime.o radeon_uvd.o
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si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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1192
drivers/gpu/drm/radeon/cik.c
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1192
drivers/gpu/drm/radeon/cik.c
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File diff suppressed because it is too large
Load diff
253
drivers/gpu/drm/radeon/cikd.h
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253
drivers/gpu/drm/radeon/cikd.h
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@ -0,0 +1,253 @@
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef CIK_H
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#define CIK_H
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#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
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#define CIK_RB_BITMAP_WIDTH_PER_SH 2
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#define DMIF_ADDR_CALC 0xC00
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x0000f000
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#define MC_SHARED_CHREMAP 0x2008
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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#define NOOFRANK_SHIFT 2
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#define NOOFRANK_MASK 0x00000004
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#define NOOFROWS_SHIFT 3
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#define NOOFROWS_MASK 0x00000038
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#define NOOFCOLS_SHIFT 6
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#define NOOFCOLS_MASK 0x000000C0
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#define CHANSIZE_SHIFT 8
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#define CHANSIZE_MASK 0x00000100
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#define NOOFGROUPS_SHIFT 12
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#define NOOFGROUPS_MASK 0x00001000
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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#define HDP_NONSURFACE_INFO 0x2C08
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#define HDP_NONSURFACE_SIZE 0x2C0C
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#define HDP_ADDR_CONFIG 0x2F48
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#define HDP_MISC_CNTL 0x2F4C
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#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
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#define BIF_FB_EN 0x5490
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#define FB_READ_EN (1 << 0)
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#define FB_WRITE_EN (1 << 1)
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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#define VGT_VTX_VECT_EJECT_REG 0x88B0
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x) << 0)
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#define VC_ONLY 0
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#define TC_ONLY 1
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#define VC_AND_TC 2
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#define AUTO_INVLD_EN(x) ((x) << 6)
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#define NO_AUTO 0
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#define ES_AUTO 1
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#define GS_AUTO 2
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#define ES_AND_GS_AUTO 3
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#define VGT_GS_VERTEX_REUSE 0x88D4
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#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
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#define INACTIVE_CUS_MASK 0xFFFF0000
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#define INACTIVE_CUS_SHIFT 16
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#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
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#define PA_CL_ENHANCE 0x8A14
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
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#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
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#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
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#define PA_SC_FIFO_SIZE 0x8BCC
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#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
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#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
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#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
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#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
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#define PA_SC_ENHANCE 0x8BF0
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#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
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#define DISABLE_PA_SC_GUIDANCE (1 << 13)
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#define SQ_CONFIG 0x8C00
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#define SX_DEBUG_1 0x9060
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#define SPI_CONFIG_CNTL 0x9100
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#define SPI_CONFIG_CNTL_1 0x913C
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#define VTX_DONE_DELAY(x) ((x) << 0)
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#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
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#define TA_CNTL_AUX 0x9508
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#define DB_DEBUG 0x9830
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#define DB_DEBUG2 0x9834
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#define DB_DEBUG3 0x9838
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define GB_ADDR_CONFIG 0x98F8
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#define NUM_PIPES(x) ((x) << 0)
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#define NUM_PIPES_MASK 0x00000007
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#define NUM_PIPES_SHIFT 0
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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
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#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
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#define PIPE_INTERLEAVE_SIZE_SHIFT 4
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#define NUM_SHADER_ENGINES(x) ((x) << 12)
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#define NUM_SHADER_ENGINES_MASK 0x00003000
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#define NUM_SHADER_ENGINES_SHIFT 12
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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
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#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
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#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
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#define ROW_SIZE(x) ((x) << 28)
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#define ROW_SIZE_MASK 0x30000000
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#define ROW_SIZE_SHIFT 28
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#define GB_TILE_MODE0 0x9910
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# define ARRAY_MODE(x) ((x) << 2)
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# define ARRAY_LINEAR_GENERAL 0
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# define ARRAY_LINEAR_ALIGNED 1
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# define ARRAY_1D_TILED_THIN1 2
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# define ARRAY_2D_TILED_THIN1 4
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# define ARRAY_PRT_TILED_THIN1 5
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# define ARRAY_PRT_2D_TILED_THIN1 6
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# define PIPE_CONFIG(x) ((x) << 6)
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# define ADDR_SURF_P2 0
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# define ADDR_SURF_P4_8x16 4
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# define ADDR_SURF_P4_16x16 5
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# define ADDR_SURF_P4_16x32 6
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# define ADDR_SURF_P4_32x32 7
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# define ADDR_SURF_P8_16x16_8x16 8
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# define ADDR_SURF_P8_16x32_8x16 9
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# define ADDR_SURF_P8_32x32_8x16 10
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# define ADDR_SURF_P8_16x32_16x16 11
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# define ADDR_SURF_P8_32x32_16x16 12
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# define ADDR_SURF_P8_32x32_16x32 13
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# define ADDR_SURF_P8_32x64_32x32 14
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# define TILE_SPLIT(x) ((x) << 11)
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# define ADDR_SURF_TILE_SPLIT_64B 0
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# define ADDR_SURF_TILE_SPLIT_128B 1
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# define ADDR_SURF_TILE_SPLIT_256B 2
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# define ADDR_SURF_TILE_SPLIT_512B 3
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# define ADDR_SURF_TILE_SPLIT_1KB 4
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# define ADDR_SURF_TILE_SPLIT_2KB 5
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# define ADDR_SURF_TILE_SPLIT_4KB 6
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# define MICRO_TILE_MODE_NEW(x) ((x) << 22)
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# define ADDR_SURF_DISPLAY_MICRO_TILING 0
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# define ADDR_SURF_THIN_MICRO_TILING 1
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# define ADDR_SURF_DEPTH_MICRO_TILING 2
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# define ADDR_SURF_ROTATED_MICRO_TILING 3
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# define SAMPLE_SPLIT(x) ((x) << 25)
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# define ADDR_SURF_SAMPLE_SPLIT_1 0
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# define ADDR_SURF_SAMPLE_SPLIT_2 1
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# define ADDR_SURF_SAMPLE_SPLIT_4 2
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# define ADDR_SURF_SAMPLE_SPLIT_8 3
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#define GB_MACROTILE_MODE0 0x9990
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# define BANK_WIDTH(x) ((x) << 0)
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# define ADDR_SURF_BANK_WIDTH_1 0
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# define ADDR_SURF_BANK_WIDTH_2 1
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# define ADDR_SURF_BANK_WIDTH_4 2
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# define ADDR_SURF_BANK_WIDTH_8 3
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# define BANK_HEIGHT(x) ((x) << 2)
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# define ADDR_SURF_BANK_HEIGHT_1 0
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# define ADDR_SURF_BANK_HEIGHT_2 1
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# define ADDR_SURF_BANK_HEIGHT_4 2
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# define ADDR_SURF_BANK_HEIGHT_8 3
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# define MACRO_TILE_ASPECT(x) ((x) << 4)
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# define ADDR_SURF_MACRO_ASPECT_1 0
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# define ADDR_SURF_MACRO_ASPECT_2 1
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# define ADDR_SURF_MACRO_ASPECT_4 2
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# define ADDR_SURF_MACRO_ASPECT_8 3
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# define NUM_BANKS(x) ((x) << 6)
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# define ADDR_SURF_2_BANK 0
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# define ADDR_SURF_4_BANK 1
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# define ADDR_SURF_8_BANK 2
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# define ADDR_SURF_16_BANK 3
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#define CB_HW_CONTROL 0x9A10
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#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
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#define BACKEND_DISABLE_MASK 0x00FF0000
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#define BACKEND_DISABLE_SHIFT 16
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#define TCP_CHAN_STEER_LO 0xac0c
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#define TCP_CHAN_STEER_HI 0xac10
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#define PA_SC_RASTER_CONFIG 0x28350
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# define RASTER_CONFIG_RB_MAP_0 0
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# define RASTER_CONFIG_RB_MAP_1 1
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# define RASTER_CONFIG_RB_MAP_2 2
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# define RASTER_CONFIG_RB_MAP_3 3
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#define GRBM_GFX_INDEX 0x30800
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SH_INDEX(x) ((x) << 8)
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#define SE_INDEX(x) ((x) << 16)
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#define SH_BROADCAST_WRITES (1 << 29)
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#define INSTANCE_BROADCAST_WRITES (1 << 30)
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#define SE_BROADCAST_WRITES (1 << 31)
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#define VGT_ESGS_RING_SIZE 0x30900
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#define VGT_GSVS_RING_SIZE 0x30904
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#define VGT_PRIMITIVE_TYPE 0x30908
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#define VGT_INDEX_TYPE 0x3090C
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#define VGT_NUM_INDICES 0x30930
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#define VGT_NUM_INSTANCES 0x30934
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#define VGT_TF_RING_SIZE 0x30938
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#define VGT_HS_OFFCHIP_PARAM 0x3093C
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#define VGT_TF_MEMORY_BASE 0x30940
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#define PA_SU_LINE_STIPPLE_VALUE 0x30a00
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#define PA_SC_LINE_STIPPLE_STATE 0x30a04
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#define SQC_CACHES 0x30d20
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#define CP_PERFMON_CNTL 0x36020
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#define CGTS_TCC_DISABLE 0x3c00c
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#define CGTS_USER_TCC_DISABLE 0x3c010
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#define TCC_DISABLE_MASK 0xFFFF0000
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#define TCC_DISABLE_SHIFT 16
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#endif
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@ -1505,6 +1505,35 @@ struct si_asic {
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uint32_t tile_mode_array[32];
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};
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struct cik_asic {
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unsigned max_shader_engines;
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unsigned max_tile_pipes;
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unsigned max_cu_per_sh;
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unsigned max_sh_per_se;
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unsigned max_backends_per_se;
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unsigned max_texture_channel_caches;
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unsigned max_gprs;
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unsigned max_gs_threads;
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unsigned max_hw_contexts;
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unsigned sc_prim_fifo_size_frontend;
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unsigned sc_prim_fifo_size_backend;
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unsigned sc_hiz_tile_fifo_size;
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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unsigned num_backends_per_se;
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unsigned backend_disable_mask_per_asic;
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unsigned backend_map;
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unsigned num_texture_channel_caches;
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unsigned mem_max_burst_length_bytes;
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unsigned mem_row_size_in_kb;
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unsigned shader_engine_tile_size;
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unsigned num_gpus;
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unsigned multi_gpu_tile_size;
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unsigned tile_config;
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};
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union radeon_asic_config {
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struct r300_asic r300;
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struct r100_asic r100;
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struct evergreen_asic evergreen;
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struct cayman_asic cayman;
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struct si_asic si;
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struct cik_asic cik;
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};
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/*
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