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NXP/FSL SoC driver updates for v5.1 take4

DPIO driver
 - Add support for cache stashing and enable it in dpaa2-eth driver
 
 GUTS driver
 - Make fsl_guts_get_svr() API internal in favor of more generic
   soc_device_match()
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Merge tag 'soc-fsl-next-v5.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers

NXP/FSL SoC driver updates for v5.1 take4

DPIO driver
- Add support for cache stashing and enable it in dpaa2-eth driver

GUTS driver
- Make fsl_guts_get_svr() API internal in favor of more generic
  soc_device_match()

* tag 'soc-fsl-next-v5.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
  dpaa2-eth: configure the cache stashing amount on a queue
  soc: fsl: dpio: configure cache stashing destination
  soc: fsl: dpio: enable frame data cache stashing per software portal
  soc: fsl: guts: make fsl_guts_get_svr() static

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hifive-unleashed-5.1
Arnd Bergmann 2019-03-01 15:03:50 +01:00
commit 8ceb820b69
9 changed files with 88 additions and 7 deletions

View File

@ -2303,9 +2303,14 @@ static int setup_rx_flow(struct dpaa2_eth_priv *priv,
queue.destination.type = DPNI_DEST_DPCON;
queue.destination.priority = 1;
queue.user_context = (u64)(uintptr_t)fq;
queue.flc.stash_control = 1;
queue.flc.value &= 0xFFFFFFFFFFFFFFC0;
/* 01 01 00 - data, annotation, flow context */
queue.flc.value |= 0x14;
err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
DPNI_QUEUE_RX, 0, fq->flowid,
DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST |
DPNI_QUEUE_OPT_FLC,
&queue);
if (err) {
dev_err(dev, "dpni_set_queue(RX) failed\n");

View File

@ -22,6 +22,7 @@ config FSL_GUTS
config FSL_MC_DPIO
tristate "QorIQ DPAA2 DPIO driver"
depends on FSL_MC_BUS
select SOC_BUS
help
Driver for the DPAA2 DPIO object. A DPIO provides queue and
buffer management facilities for software to interact with

View File

@ -26,6 +26,7 @@
#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
#define DPIO_CMDID_RESET DPIO_CMD(0x005)
#define DPIO_CMDID_SET_STASHING_DEST DPIO_CMD(0x120)
struct dpio_cmd_open {
__le32 dpio_id;
@ -47,4 +48,8 @@ struct dpio_rsp_get_attr {
__le32 qbman_version;
};
struct dpio_stashing_dest {
u8 sdest;
};
#endif /* _FSL_DPIO_CMD_H */

View File

@ -14,6 +14,7 @@
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/sys_soc.h>
#include <linux/fsl/mc.h>
#include <soc/fsl/dpaa2-io.h>
@ -32,6 +33,46 @@ struct dpio_priv {
static cpumask_var_t cpus_unused_mask;
static const struct soc_device_attribute ls1088a_soc[] = {
{.family = "QorIQ LS1088A"},
{ /* sentinel */ }
};
static const struct soc_device_attribute ls2080a_soc[] = {
{.family = "QorIQ LS2080A"},
{ /* sentinel */ }
};
static const struct soc_device_attribute ls2088a_soc[] = {
{.family = "QorIQ LS2088A"},
{ /* sentinel */ }
};
static const struct soc_device_attribute lx2160a_soc[] = {
{.family = "QorIQ LX2160A"},
{ /* sentinel */ }
};
static int dpaa2_dpio_get_cluster_sdest(struct fsl_mc_device *dpio_dev, int cpu)
{
int cluster_base, cluster_size;
if (soc_device_match(ls1088a_soc)) {
cluster_base = 2;
cluster_size = 4;
} else if (soc_device_match(ls2080a_soc) ||
soc_device_match(ls2088a_soc) ||
soc_device_match(lx2160a_soc)) {
cluster_base = 0;
cluster_size = 2;
} else {
dev_err(&dpio_dev->dev, "unknown SoC version\n");
return -1;
}
return cluster_base + cpu / cluster_size;
}
static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
{
struct device *dev = (struct device *)arg;
@ -89,6 +130,7 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
int err = -ENOMEM;
struct device *dev = &dpio_dev->dev;
int possible_next_cpu;
int sdest;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@ -145,6 +187,16 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
desc.cpu = possible_next_cpu;
cpumask_clear_cpu(possible_next_cpu, cpus_unused_mask);
sdest = dpaa2_dpio_get_cluster_sdest(dpio_dev, desc.cpu);
if (sdest >= 0) {
err = dpio_set_stashing_destination(dpio_dev->mc_io, 0,
dpio_dev->mc_handle,
sdest);
if (err)
dev_err(dev, "dpio_set_stashing_destination failed for cpu%d\n",
desc.cpu);
}
/*
* Set the CENA regs to be the cache inhibited area of the portal to
* avoid coherency issues if a user migrates to another core.

View File

@ -166,6 +166,22 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
return 0;
}
int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 sdest)
{
struct fsl_mc_command cmd = { 0 };
struct dpio_stashing_dest *dpio_cmd;
cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_STASHING_DEST,
cmd_flags, token);
dpio_cmd = (struct dpio_stashing_dest *)cmd.params;
dpio_cmd->sdest = sdest;
return mc_send_command(mc_io, &cmd);
}
/**
* dpio_get_api_version - Get Data Path I/O API version
* @mc_io: Pointer to MC portal's DPIO object

View File

@ -75,6 +75,11 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
u16 token,
struct dpio_attr *attr);
int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
u8 dest);
int dpio_get_api_version(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 *major_ver,

View File

@ -169,9 +169,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
3, /* RPM: Valid bit mode, RCR in array mode */
2, /* DCM: Discrete consumption ack mode */
3, /* EPM: Valid bit mode, EQCR in array mode */
0, /* mem stashing drop enable == FALSE */
1, /* mem stashing drop enable == TRUE */
1, /* mem stashing priority == TRUE */
0, /* mem stashing enable == FALSE */
1, /* mem stashing enable == TRUE */
1, /* dequeue stashing priority == TRUE */
0, /* dequeue stashing enable == FALSE */
0); /* EQCR_CI stashing priority == FALSE */

View File

@ -115,7 +115,7 @@ static const struct fsl_soc_die_attr *fsl_soc_die_match(
return NULL;
}
u32 fsl_guts_get_svr(void)
static u32 fsl_guts_get_svr(void)
{
u32 svr = 0;
@ -129,7 +129,6 @@ u32 fsl_guts_get_svr(void)
return svr;
}
EXPORT_SYMBOL(fsl_guts_get_svr);
static int fsl_guts_probe(struct platform_device *pdev)
{

View File

@ -135,8 +135,6 @@ struct ccsr_guts {
u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
u32 fsl_guts_get_svr(void);
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))