perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP
CBOX counters are increased to 48b on HSX. Correct the MSR address for HSWEP_U_MSR_PMON_CTR0 and HSWEP_U_MSR_PMON_CTL0. See specification in: http://www.intel.com/content/www/us/en/processors/xeon/ xeon-e5-v3-uncore-performance-monitoring.html Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1432645835-7918-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -164,8 +164,8 @@
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((1ULL << (n)) - 1)))
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/* Haswell-EP Ubox */
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#define HSWEP_U_MSR_PMON_CTR0 0x705
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#define HSWEP_U_MSR_PMON_CTL0 0x709
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#define HSWEP_U_MSR_PMON_CTR0 0x709
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#define HSWEP_U_MSR_PMON_CTL0 0x705
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#define HSWEP_U_MSR_PMON_FILTER 0x707
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#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
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@ -1914,7 +1914,7 @@ static struct intel_uncore_type hswep_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 18,
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.perf_ctr_bits = 44,
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.perf_ctr_bits = 48,
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.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
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.perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
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.event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
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