pinctrl: tegra: driver layout/consistency fixes
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -1547,6 +1547,7 @@ static struct tegra_function tegra114_functions[] = {
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_BIT_Y(b) (b)
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#define PINGROUP_BIT_Y(b) (b)
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@ -1572,20 +1573,17 @@ static struct tegra_function tegra114_functions[] = {
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.tri_reg = PINGROUP_REG(r), \
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.tri_reg = PINGROUP_REG(r), \
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.tri_bank = 1, \
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.tri_bank = 1, \
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.tri_bit = 4, \
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.tri_bit = 4, \
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.einput_bit = PINGROUP_BIT_Y(5), \
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.einput_bit = 5, \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.lock_bit = PINGROUP_BIT_Y(7), \
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.lock_bit = 7, \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
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.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
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.drv_reg = -1, \
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.drv_reg = -1, \
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}
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}
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
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drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
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slwf_b, slwf_w, drvtype) \
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drvdn_b, drvdn_w, drvup_b, drvup_w, \
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slwr_b, slwr_w, slwf_b, slwf_w, \
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drvtype) \
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{ \
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{ \
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.name = "drive_" #pg_name, \
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.name = "drive_" #pg_name, \
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.pins = drive_##pg_name##_pins, \
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.pins = drive_##pg_name##_pins, \
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@ -1536,6 +1536,7 @@ enum tegra_mux {
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TEGRA_MUX_CLK,
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TEGRA_MUX_CLK,
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TEGRA_MUX_CLK12,
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TEGRA_MUX_CLK12,
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TEGRA_MUX_CPU,
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TEGRA_MUX_CPU,
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TEGRA_MUX_CSI,
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TEGRA_MUX_DAP,
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TEGRA_MUX_DAP,
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TEGRA_MUX_DAP1,
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TEGRA_MUX_DAP1,
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TEGRA_MUX_DAP2,
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TEGRA_MUX_DAP2,
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@ -1544,6 +1545,7 @@ enum tegra_mux {
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TEGRA_MUX_DISPLAYA_ALT,
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TEGRA_MUX_DISPLAYA_ALT,
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TEGRA_MUX_DISPLAYB,
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TEGRA_MUX_DISPLAYB,
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TEGRA_MUX_DP,
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TEGRA_MUX_DP,
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TEGRA_MUX_DSI_B,
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TEGRA_MUX_DTV,
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TEGRA_MUX_DTV,
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TEGRA_MUX_EXTPERIPH1,
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TEGRA_MUX_EXTPERIPH1,
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TEGRA_MUX_EXTPERIPH2,
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TEGRA_MUX_EXTPERIPH2,
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@ -1613,8 +1615,6 @@ enum tegra_mux {
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TEGRA_MUX_VI_ALT3,
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TEGRA_MUX_VI_ALT3,
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TEGRA_MUX_VIMCLK2,
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TEGRA_MUX_VIMCLK2,
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TEGRA_MUX_VIMCLK2_ALT,
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TEGRA_MUX_VIMCLK2_ALT,
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TEGRA_MUX_CSI,
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TEGRA_MUX_DSI_B,
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};
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};
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#define FUNCTION(fname) \
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#define FUNCTION(fname) \
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@ -1630,6 +1630,7 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(clk),
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FUNCTION(clk),
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FUNCTION(clk12),
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FUNCTION(clk12),
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FUNCTION(cpu),
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FUNCTION(cpu),
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FUNCTION(csi),
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FUNCTION(dap),
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FUNCTION(dap),
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FUNCTION(dap1),
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FUNCTION(dap1),
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FUNCTION(dap2),
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FUNCTION(dap2),
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@ -1638,6 +1639,7 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(displaya_alt),
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FUNCTION(displaya_alt),
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FUNCTION(displayb),
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FUNCTION(displayb),
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FUNCTION(dp),
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FUNCTION(dp),
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FUNCTION(dsi_b),
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FUNCTION(dtv),
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FUNCTION(dtv),
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FUNCTION(extperiph1),
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FUNCTION(extperiph1),
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FUNCTION(extperiph2),
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FUNCTION(extperiph2),
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@ -1707,15 +1709,15 @@ static struct tegra_function tegra124_functions[] = {
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FUNCTION(vi_alt3),
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FUNCTION(vi_alt3),
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FUNCTION(vimclk2),
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FUNCTION(vimclk2),
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FUNCTION(vimclk2_alt),
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FUNCTION(vimclk2_alt),
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FUNCTION(csi),
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FUNCTION(dsi_b),
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};
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};
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
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#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
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#define PINGROUP_BIT_Y(b) (b)
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#define PINGROUP_BIT_Y(b) (b)
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#define PINGROUP_BIT_N(b) (-1)
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#define PINGROUP_BIT_N(b) (-1)
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@ -1740,20 +1742,17 @@ static struct tegra_function tegra124_functions[] = {
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.tri_reg = PINGROUP_REG(r), \
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.tri_reg = PINGROUP_REG(r), \
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.tri_bank = 1, \
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.tri_bank = 1, \
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.tri_bit = 4, \
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.tri_bit = 4, \
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.einput_bit = PINGROUP_BIT_Y(5), \
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.einput_bit = 5, \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.lock_bit = PINGROUP_BIT_Y(7), \
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.lock_bit = 7, \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
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.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
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.drv_reg = -1, \
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.drv_reg = -1, \
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}
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}
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
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drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
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slwf_b, slwf_w, drvtype) \
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drvdn_b, drvdn_w, drvup_b, drvup_w, \
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slwr_b, slwr_w, slwf_b, slwf_w, \
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drvtype) \
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{ \
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{ \
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.name = "drive_" #pg_name, \
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.name = "drive_" #pg_name, \
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.pins = drive_##pg_name##_pins, \
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.pins = drive_##pg_name##_pins, \
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@ -1782,8 +1781,6 @@ static struct tegra_function tegra124_functions[] = {
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.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
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.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
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}
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}
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#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
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#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
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#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
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{ \
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{ \
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.name = "mipi_pad_ctrl_" #pg_name, \
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.name = "mipi_pad_ctrl_" #pg_name, \
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@ -2044,8 +2041,8 @@ static const struct tegra_pingroup tegra124_groups[] = {
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DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
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DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
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DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
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DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
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/* pg_name, r b f0, f1 */
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/* pg_name, r, b, f0, f1 */
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MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
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MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
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};
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};
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static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
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static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
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@ -2108,70 +2108,69 @@ static struct tegra_function tegra30_functions[] = {
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define PINGROUP_REG_A 0x3000 /* bank 1 */
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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#define PINGROUP_BIT_Y(b) (b)
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#define PINGROUP_BIT_Y(b) (b)
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#define PINGROUP_BIT_N(b) (-1)
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#define PINGROUP_BIT_N(b) (-1)
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#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
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#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
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{ \
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{ \
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.name = #pg_name, \
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.name = #pg_name, \
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.pins = pg_name##_pins, \
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.pins = pg_name##_pins, \
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.npins = ARRAY_SIZE(pg_name##_pins), \
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.npins = ARRAY_SIZE(pg_name##_pins), \
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.funcs = { \
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.funcs = { \
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TEGRA_MUX_##f0, \
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TEGRA_MUX_##f0, \
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TEGRA_MUX_##f1, \
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TEGRA_MUX_##f1, \
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TEGRA_MUX_##f2, \
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TEGRA_MUX_##f2, \
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TEGRA_MUX_##f3, \
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TEGRA_MUX_##f3, \
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}, \
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}, \
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.mux_reg = PINGROUP_REG(r), \
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.mux_reg = PINGROUP_REG(r), \
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.mux_bank = 1, \
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.mux_bank = 1, \
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.mux_bit = 0, \
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.mux_bit = 0, \
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.pupd_reg = PINGROUP_REG(r), \
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.pupd_reg = PINGROUP_REG(r), \
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.pupd_bank = 1, \
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.pupd_bank = 1, \
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.pupd_bit = 2, \
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.pupd_bit = 2, \
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.tri_reg = PINGROUP_REG(r), \
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.tri_reg = PINGROUP_REG(r), \
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.tri_bank = 1, \
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.tri_bank = 1, \
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.tri_bit = 4, \
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.tri_bit = 4, \
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.einput_bit = PINGROUP_BIT_Y(5), \
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.einput_bit = 5, \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.odrain_bit = PINGROUP_BIT_##od(6), \
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.lock_bit = PINGROUP_BIT_Y(7), \
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.lock_bit = 7, \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.ioreset_bit = PINGROUP_BIT_##ior(8), \
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.rcv_sel_bit = -1, \
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.rcv_sel_bit = -1, \
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.drv_reg = -1, \
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.drv_reg = -1, \
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}
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}
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#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
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drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
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slwf_b, slwf_w) \
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drvdn_b, drvdn_w, drvup_b, drvup_w, \
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{ \
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slwr_b, slwr_w, slwf_b, slwf_w) \
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.name = "drive_" #pg_name, \
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{ \
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.pins = drive_##pg_name##_pins, \
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.name = "drive_" #pg_name, \
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.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
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.pins = drive_##pg_name##_pins, \
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.mux_reg = -1, \
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.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
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.pupd_reg = -1, \
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.mux_reg = -1, \
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.tri_reg = -1, \
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.pupd_reg = -1, \
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.einput_bit = -1, \
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.tri_reg = -1, \
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.odrain_bit = -1, \
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.einput_bit = -1, \
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.lock_bit = -1, \
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.odrain_bit = -1, \
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.ioreset_bit = -1, \
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.lock_bit = -1, \
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.rcv_sel_bit = -1, \
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.ioreset_bit = -1, \
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.drv_reg = DRV_PINGROUP_REG(r), \
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.rcv_sel_bit = -1, \
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.drv_bank = 0, \
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.drv_reg = DRV_PINGROUP_REG(r), \
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.hsm_bit = hsm_b, \
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.drv_bank = 0, \
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.schmitt_bit = schmitt_b, \
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.hsm_bit = hsm_b, \
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.lpmd_bit = lpmd_b, \
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.schmitt_bit = schmitt_b, \
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.drvdn_bit = drvdn_b, \
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.lpmd_bit = lpmd_b, \
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.drvdn_width = drvdn_w, \
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.drvdn_bit = drvdn_b, \
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.drvup_bit = drvup_b, \
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.drvdn_width = drvdn_w, \
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.drvup_width = drvup_w, \
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.drvup_bit = drvup_b, \
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.slwr_bit = slwr_b, \
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.drvup_width = drvup_w, \
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.slwr_width = slwr_w, \
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.slwr_bit = slwr_b, \
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.slwf_bit = slwf_b, \
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.slwr_width = slwr_w, \
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.slwf_width = slwf_w, \
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.slwf_bit = slwf_b, \
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.drvtype_bit = -1, \
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.slwf_width = slwf_w, \
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.drvtype_bit = -1, \
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}
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}
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static const struct tegra_pingroup tegra30_groups[] = {
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static const struct tegra_pingroup tegra30_groups[] = {
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