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[MIPS] kgdb: Remove existing implementation 

This patch explicitly removes the kgdb implementation, for mips which
is intended to be followed by a patch that adds a kgdb implementation
for MIPS that makes use of the kgdb core in the kernel.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Jason Wessel 2008-07-29 15:58:52 -05:00 committed by Ralf Baechle
parent 8f8da9adeb
commit 8d60a903d9
59 changed files with 4 additions and 3134 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/mips/Kconfig
View File

@ -34,7 +34,6 @@ config BASLER_EXCITE
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_KGDB
help
The eXcite is a smart camera platform manufactured by
Basler Vision Technologies AG.
@ -280,7 +279,6 @@ config PMC_MSP
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_KGDB
select IRQ_CPU
select SERIAL_8250
select SERIAL_8250_CONSOLE
@ -306,7 +304,6 @@ config PMC_YOSEMITE
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_SMP
help
Yosemite is an evaluation board for the RM9000x2 processor
@ -359,7 +356,6 @@ config SGI_IP27
select SYS_HAS_CPU_R10000
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
select GENERIC_HARDIRQS_NO__DO_IRQ
@ -475,7 +471,6 @@ config SIBYTE_SWARM
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
select ZONE_DMA32 if 64BIT
@ -868,7 +863,6 @@ config SOC_PNX8550
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_HARDIRQS_NO__DO_IRQ
select SYS_SUPPORTS_KGDB
select GENERIC_GPIO
config SWAP_IO_SPACE

22
arch/mips/Kconfig.debug
View File

@ -34,28 +34,6 @@ config SMTC_IDLE_HOOK_DEBUG
arch/mips/kernel/smtc.c. This debugging option result in significant
overhead so should be disabled in production kernels.
config KGDB
bool "Remote GDB kernel debugging"
depends on DEBUG_KERNEL && SYS_SUPPORTS_KGDB
select DEBUG_INFO
help
If you say Y here, it will be possible to remotely debug the MIPS
kernel using gdb. This enlarges your kernel image disk size by
several megabytes and requires a machine with more than 16 MB,
better 32 MB RAM to avoid excessive linking time. This is only
useful for kernel hackers. If unsure, say N.
config SYS_SUPPORTS_KGDB
bool
config GDB_CONSOLE
bool "Console output to GDB"
depends on KGDB
help
If you are using GDB for remote debugging over a serial port and
would like kernel messages to be formatted into GDB $O packets so
that GDB prints them as program output, say 'Y'.
config SB1XXX_CORELIS
bool "Corelis Debugger"
depends on SIBYTE_SB1xxx_SOC

1
arch/mips/au1000/Kconfig
View File

@ -134,4 +134,3 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select SYS_SUPPORTS_KGDB

1
arch/mips/au1000/common/Makefile
View File

@ -9,7 +9,6 @@ obj-y += prom.o irq.o puts.o time.o reset.o \
au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
sleeper.o cputable.o dma.o dbdma.o gpio.o
obj-$(CONFIG_KGDB) += dbg_io.o
obj-$(CONFIG_PCI) += pci.o
EXTRA_CFLAGS += -Werror

109
arch/mips/au1000/common/dbg_io.c
View File

@ -1,109 +0,0 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1000.h>
#ifdef CONFIG_KGDB
/*
* FIXME the user should be able to select the
* uart to be used for debugging.
*/
#define DEBUG_BASE UART_DEBUG_BASE
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
#define UART_RX 0 /* Receive buffer */
#define UART_TX 4 /* Transmit buffer */
#define UART_IER 8 /* Interrupt Enable Register */
#define UART_IIR 0xC /* Interrupt ID Register */
#define UART_FCR 0x10 /* FIFO Control Register */
#define UART_LCR 0x14 /* Line Control Register */
#define UART_MCR 0x18 /* Modem Control Register */
#define UART_LSR 0x1C /* Line Status Register */
#define UART_MSR 0x20 /* Modem Status Register */
#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
#define UART_MOD_CNTRL 0x100 /* Module Control */
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
extern unsigned long calc_clock(void);
void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
{
if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
UART16550_WRITE(UART_MOD_CNTRL, 3);
calc_clock();
/* disable interrupts */
UART16550_WRITE(UART_IER, 0);
/* set up baud rate */
{
u32 divisor;
/* set divisor */
divisor = get_au1x00_uart_baud_base() / baud;
UART16550_WRITE(UART_CLK, divisor & 0xffff);
}
/* set data format */
UART16550_WRITE(UART_LCR, (data | parity | stop));
}
static int remoteDebugInitialized;
u8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_115200,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE,
UART16550_STOP_1BIT);
}
while ((UART16550_READ(UART_LSR) & 0x1) == 0);
return UART16550_READ(UART_RX);
}
int putDebugChar(u8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_115200,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE,
UART16550_STOP_1BIT);
}
while ((UART16550_READ(UART_LSR) & 0x40) == 0);
UART16550_WRITE(UART_TX, byte);
return 1;
}
#endif

1
arch/mips/basler/excite/Makefile
View File

@ -5,5 +5,4 @@
obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
excite_device.o excite_procfs.o
obj-$(CONFIG_KGDB) += excite_dbg_io.o
obj-m += excite_iodev.o

121
arch/mips/basler/excite/excite_dbg_io.c
View File

@ -1,121 +0,0 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/gdb-stub.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
#error Debug port used by serial driver
#endif
#define UART_CLK 25000000
#define BASE_BAUD (UART_CLK / 16)
#define REGISTER_BASE_0 0x0208UL
#define REGISTER_BASE_1 0x0238UL
#define REGISTER_BASE_DBG REGISTER_BASE_1
#define CPRR 0x0004
#define UACFG 0x0200
#define UAINTS 0x0204
#define UARBR (REGISTER_BASE_DBG + 0x0000)
#define UATHR (REGISTER_BASE_DBG + 0x0004)
#define UADLL (REGISTER_BASE_DBG + 0x0008)
#define UAIER (REGISTER_BASE_DBG + 0x000c)
#define UADLH (REGISTER_BASE_DBG + 0x0010)
#define UAIIR (REGISTER_BASE_DBG + 0x0014)
#define UAFCR (REGISTER_BASE_DBG + 0x0018)
#define UALCR (REGISTER_BASE_DBG + 0x001c)
#define UAMCR (REGISTER_BASE_DBG + 0x0020)
#define UALSR (REGISTER_BASE_DBG + 0x0024)
#define UAMSR (REGISTER_BASE_DBG + 0x0028)
#define UASCR (REGISTER_BASE_DBG + 0x002c)
#define PARITY_NONE 0
#define PARITY_ODD 0x08
#define PARITY_EVEN 0x18
#define PARITY_MARK 0x28
#define PARITY_SPACE 0x38
#define DATA_5BIT 0x0
#define DATA_6BIT 0x1
#define DATA_7BIT 0x2
#define DATA_8BIT 0x3
#define STOP_1BIT 0x0
#define STOP_2BIT 0x4
#define BAUD_DBG 57600
#define PARITY_DBG PARITY_NONE
#define DATA_DBG DATA_8BIT
#define STOP_DBG STOP_1BIT
/* Initialize the serial port for KGDB debugging */
void __init excite_kgdb_init(void)
{
const u32 divisor = BASE_BAUD / BAUD_DBG;
/* Take the UART out of reset */
titan_writel(0x00ff1cff, CPRR);
titan_writel(0x00000000, UACFG);
titan_writel(0x00000002, UACFG);
titan_writel(0x0, UALCR);
titan_writel(0x0, UAIER);
/* Disable FIFOs */
titan_writel(0x00, UAFCR);
titan_writel(0x80, UALCR);
titan_writel(divisor & 0xff, UADLL);
titan_writel((divisor & 0xff00) >> 8, UADLH);
titan_writel(0x0, UALCR);
titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
/* Enable receiver interrupt */
titan_readl(UARBR);
titan_writel(0x1, UAIER);
}
int getDebugChar(void)
{
while (!(titan_readl(UALSR) & 0x1));
return titan_readl(UARBR);
}
int putDebugChar(int data)
{
while (!(titan_readl(UALSR) & 0x20));
titan_writel(data, UATHR);
return 1;
}
/* KGDB interrupt handler */
asmlinkage void excite_kgdb_inthdl(void)
{
if (unlikely(
((titan_readl(UAIIR) & 0x7) == 4)
&& ((titan_readl(UARBR) & 0xff) == 0x3)))
set_async_breakpoint(&regs->cp0_epc);
}

7
arch/mips/basler/excite/excite_irq.c
View File

@ -50,10 +50,6 @@ void __init arch_init_irq(void)
mips_cpu_irq_init();
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
#ifdef CONFIG_KGDB
excite_kgdb_init();
#endif
}
asmlinkage void plat_irq_dispatch(void)
@ -90,9 +86,6 @@ asmlinkage void plat_irq_dispatch(void)
msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
if ((pending & (1 << TITAN_IRQ)) && msgint) {
ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
#if defined(CONFIG_KGDB)
excite_kgdb_inthdl();
#endif
do_IRQ(TITAN_IRQ);
return;
}

4
arch/mips/basler/excite/excite_setup.c
View File

@ -95,13 +95,13 @@ static int __init excite_init_console(void)
/* Take the DUART out of reset */
titan_writel(0x00ff1cff, CPRR);
#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
/* Enable both ports */
titan_writel(MASK_SER0 | MASK_SER1, UACFG);
#else
/* Enable port #0 only */
titan_writel(MASK_SER0, UACFG);
#endif /* defined(CONFIG_KGDB) */
#endif
/*
* Set up serial port #0. Do not use autodetection; the result is

1
arch/mips/configs/db1000_defconfig
View File

@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/db1100_defconfig
View File

@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/db1200_defconfig
View File

@ -1174,7 +1174,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE="mem=48M"
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/db1500_defconfig
View File

@ -1392,7 +1392,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/db1550_defconfig
View File

@ -1209,7 +1209,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/excite_defconfig
View File

@ -1269,7 +1269,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/ip27_defconfig
View File

@ -943,7 +943,6 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

2
arch/mips/configs/msp71xx_defconfig
View File

@ -1415,8 +1415,6 @@ CONFIG_FORCED_INLINING=y
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_KGDB is not set
CONFIG_SYS_SUPPORTS_KGDB=y
# CONFIG_RUNTIME_DEBUG is not set
# CONFIG_MIPS_UNCACHED is not set

1
arch/mips/configs/mtx1_defconfig
View File

@ -3020,7 +3020,6 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/pb1100_defconfig
View File

@ -1085,7 +1085,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/pb1500_defconfig
View File

@ -1202,7 +1202,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/pb1550_defconfig
View File

@ -1195,7 +1195,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

4
arch/mips/configs/pnx8550-jbs_defconfig
View File

@ -1216,10 +1216,8 @@ CONFIG_DEBUG_MUTEXES=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_KGDB is not set
CONFIG_SYS_SUPPORTS_KGDB=y
# CONFIG_RUNTIME_DEBUG is not set
#

4
arch/mips/configs/pnx8550-stb810_defconfig
View File

@ -1206,10 +1206,8 @@ CONFIG_DEBUG_SLAB=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_KGDB is not set
CONFIG_SYS_SUPPORTS_KGDB=y
# CONFIG_RUNTIME_DEBUG is not set
#

1
arch/mips/configs/rbtx49xx_defconfig
View File

@ -742,7 +742,6 @@ CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
#
# Security options

1
arch/mips/configs/sb1250-swarm_defconfig
View File

@ -963,7 +963,6 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
CONFIG_SYS_SUPPORTS_KGDB=y
# CONFIG_SB1XXX_CORELIS is not set
#

2
arch/mips/configs/yosemite_defconfig
View File

@ -827,8 +827,6 @@ CONFIG_FORCED_INLINING=y
CONFIG_CROSSCOMPILE=y
CONFIG_CMDLINE=""
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_KGDB is not set
CONFIG_SYS_SUPPORTS_KGDB=y
# CONFIG_RUNTIME_DEBUG is not set
#

1
arch/mips/emma2rh/markeins/platform.c
View File

@ -34,7 +34,6 @@
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/traps.h>
#include <asm/debug.h>

1
arch/mips/emma2rh/markeins/setup.c
View File

@ -41,7 +41,6 @@
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/traps.h>
#include <asm/debug.h>

1
arch/mips/kernel/Makefile
View File

@ -71,7 +71,6 @@ obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o
obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o
obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_64BIT) += cpu-bugs64.o

394
arch/mips/kernel/gdb-low.S
View File

@ -1,394 +0,0 @@
/*
* gdb-low.S contains the low-level trap handler for the GDB stub.
*
* Copyright (C) 1995 Andreas Busse
*/
#include <linux/sys.h>
#include <asm/asm.h>
#include <asm/errno.h>
#include <asm/irqflags.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/gdb-stub.h>
#ifdef CONFIG_32BIT
#define DMFC0 mfc0
#define DMTC0 mtc0
#define LDC1 lwc1
#define SDC1 lwc1
#endif
#ifdef CONFIG_64BIT
#define DMFC0 dmfc0
#define DMTC0 dmtc0
#define LDC1 ldc1
#define SDC1 ldc1
#endif
/*
* [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)
* part is used to store registers and passed to exception handler.
* The upper part is reserved for "call func" feature where gdb client
* saves some of the regs, setups call frame and passes args.
*
* A trace shows about 200 bytes are used to store about half of all regs.
* The rest should be big enough for frame setup and passing args.
*/
/*
* The low level trap handler
*/
.align 5
NESTED(trap_low, GDB_FR_SIZE, sp)
.set noat
.set noreorder
mfc0 k0, CP0_STATUS
sll k0, 3 /* extract cu0 bit */
bltz k0, 1f
move k1, sp
/*
* Called from user mode, go somewhere else.
*/
mfc0 k0, CP0_CAUSE
andi k0, k0, 0x7c
#ifdef CONFIG_64BIT
dsll k0, k0, 1
#endif
PTR_L k1, saved_vectors(k0)
jr k1
nop
1:
move k0, sp
PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above
LONG_S k0, GDB_FR_REG29(sp)
LONG_S $2, GDB_FR_REG2(sp)
/*
* First save the CP0 and special registers
*/
mfc0 v0, CP0_STATUS
LONG_S v0, GDB_FR_STATUS(sp)
mfc0 v0, CP0_CAUSE
LONG_S v0, GDB_FR_CAUSE(sp)
DMFC0 v0, CP0_EPC
LONG_S v0, GDB_FR_EPC(sp)
DMFC0 v0, CP0_BADVADDR
LONG_S v0, GDB_FR_BADVADDR(sp)
mfhi v0
LONG_S v0, GDB_FR_HI(sp)
mflo v0
LONG_S v0, GDB_FR_LO(sp)
/*
* Now the integer registers
*/
LONG_S zero, GDB_FR_REG0(sp) /* I know... */
LONG_S $1, GDB_FR_REG1(sp)
/* v0 already saved */
LONG_S $3, GDB_FR_REG3(sp)
LONG_S $4, GDB_FR_REG4(sp)
LONG_S $5, GDB_FR_REG5(sp)
LONG_S $6, GDB_FR_REG6(sp)
LONG_S $7, GDB_FR_REG7(sp)
LONG_S $8, GDB_FR_REG8(sp)
LONG_S $9, GDB_FR_REG9(sp)
LONG_S $10, GDB_FR_REG10(sp)
LONG_S $11, GDB_FR_REG11(sp)
LONG_S $12, GDB_FR_REG12(sp)
LONG_S $13, GDB_FR_REG13(sp)
LONG_S $14, GDB_FR_REG14(sp)
LONG_S $15, GDB_FR_REG15(sp)
LONG_S $16, GDB_FR_REG16(sp)
LONG_S $17, GDB_FR_REG17(sp)
LONG_S $18, GDB_FR_REG18(sp)
LONG_S $19, GDB_FR_REG19(sp)
LONG_S $20, GDB_FR_REG20(sp)
LONG_S $21, GDB_FR_REG21(sp)
LONG_S $22, GDB_FR_REG22(sp)
LONG_S $23, GDB_FR_REG23(sp)
LONG_S $24, GDB_FR_REG24(sp)
LONG_S $25, GDB_FR_REG25(sp)
LONG_S $26, GDB_FR_REG26(sp)
LONG_S $27, GDB_FR_REG27(sp)
LONG_S $28, GDB_FR_REG28(sp)
/* sp already saved */
LONG_S $30, GDB_FR_REG30(sp)
LONG_S $31, GDB_FR_REG31(sp)
CLI /* disable interrupts */
TRACE_IRQS_OFF
/*
* Followed by the floating point registers
*/
mfc0 v0, CP0_STATUS /* FPU enabled? */
srl v0, v0, 16
andi v0, v0, (ST0_CU1 >> 16)
beqz v0,2f /* disabled, skip */
nop
SDC1 $0, GDB_FR_FPR0(sp)
SDC1 $1, GDB_FR_FPR1(sp)
SDC1 $2, GDB_FR_FPR2(sp)
SDC1 $3, GDB_FR_FPR3(sp)
SDC1 $4, GDB_FR_FPR4(sp)
SDC1 $5, GDB_FR_FPR5(sp)
SDC1 $6, GDB_FR_FPR6(sp)
SDC1 $7, GDB_FR_FPR7(sp)
SDC1 $8, GDB_FR_FPR8(sp)
SDC1 $9, GDB_FR_FPR9(sp)
SDC1 $10, GDB_FR_FPR10(sp)
SDC1 $11, GDB_FR_FPR11(sp)
SDC1 $12, GDB_FR_FPR12(sp)
SDC1 $13, GDB_FR_FPR13(sp)
SDC1 $14, GDB_FR_FPR14(sp)
SDC1 $15, GDB_FR_FPR15(sp)
SDC1 $16, GDB_FR_FPR16(sp)
SDC1 $17, GDB_FR_FPR17(sp)
SDC1 $18, GDB_FR_FPR18(sp)
SDC1 $19, GDB_FR_FPR19(sp)
SDC1 $20, GDB_FR_FPR20(sp)
SDC1 $21, GDB_FR_FPR21(sp)
SDC1 $22, GDB_FR_FPR22(sp)
SDC1 $23, GDB_FR_FPR23(sp)
SDC1 $24, GDB_FR_FPR24(sp)
SDC1 $25, GDB_FR_FPR25(sp)
SDC1 $26, GDB_FR_FPR26(sp)
SDC1 $27, GDB_FR_FPR27(sp)
SDC1 $28, GDB_FR_FPR28(sp)
SDC1 $29, GDB_FR_FPR29(sp)
SDC1 $30, GDB_FR_FPR30(sp)
SDC1 $31, GDB_FR_FPR31(sp)
/*
* FPU control registers
*/
cfc1 v0, CP1_STATUS
LONG_S v0, GDB_FR_FSR(sp)
cfc1 v0, CP1_REVISION
LONG_S v0, GDB_FR_FIR(sp)
/*
* Current stack frame ptr
*/
2:
LONG_S sp, GDB_FR_FRP(sp)
/*
* CP0 registers (R4000/R4400 unused registers skipped)
*/
mfc0 v0, CP0_INDEX
LONG_S v0, GDB_FR_CP0_INDEX(sp)
mfc0 v0, CP0_RANDOM
LONG_S v0, GDB_FR_CP0_RANDOM(sp)
DMFC0 v0, CP0_ENTRYLO0
LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp)
DMFC0 v0, CP0_ENTRYLO1
LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp)
DMFC0 v0, CP0_CONTEXT
LONG_S v0, GDB_FR_CP0_CONTEXT(sp)
mfc0 v0, CP0_PAGEMASK
LONG_S v0, GDB_FR_CP0_PAGEMASK(sp)
mfc0 v0, CP0_WIRED
LONG_S v0, GDB_FR_CP0_WIRED(sp)
DMFC0 v0, CP0_ENTRYHI
LONG_S v0, GDB_FR_CP0_ENTRYHI(sp)
mfc0 v0, CP0_PRID
LONG_S v0, GDB_FR_CP0_PRID(sp)
.set at
/*
* Continue with the higher level handler
*/
move a0,sp
jal handle_exception
nop
/*
* Restore all writable registers, in reverse order
*/
.set noat
LONG_L v0, GDB_FR_CP0_ENTRYHI(sp)
LONG_L v1, GDB_FR_CP0_WIRED(sp)
DMTC0 v0, CP0_ENTRYHI
mtc0 v1, CP0_WIRED
LONG_L v0, GDB_FR_CP0_PAGEMASK(sp)
LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp)
mtc0 v0, CP0_PAGEMASK
DMTC0 v1, CP0_ENTRYLO1
LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp)
LONG_L v1, GDB_FR_CP0_INDEX(sp)
DMTC0 v0, CP0_ENTRYLO0
LONG_L v0, GDB_FR_CP0_CONTEXT(sp)
mtc0 v1, CP0_INDEX
DMTC0 v0, CP0_CONTEXT
/*
* Next, the floating point registers
*/
mfc0 v0, CP0_STATUS /* check if the FPU is enabled */
srl v0, v0, 16
andi v0, v0, (ST0_CU1 >> 16)
beqz v0, 3f /* disabled, skip */
nop
LDC1 $31, GDB_FR_FPR31(sp)
LDC1 $30, GDB_FR_FPR30(sp)
LDC1 $29, GDB_FR_FPR29(sp)
LDC1 $28, GDB_FR_FPR28(sp)
LDC1 $27, GDB_FR_FPR27(sp)
LDC1 $26, GDB_FR_FPR26(sp)
LDC1 $25, GDB_FR_FPR25(sp)
LDC1 $24, GDB_FR_FPR24(sp)
LDC1 $23, GDB_FR_FPR23(sp)
LDC1 $22, GDB_FR_FPR22(sp)
LDC1 $21, GDB_FR_FPR21(sp)
LDC1 $20, GDB_FR_FPR20(sp)
LDC1 $19, GDB_FR_FPR19(sp)
LDC1 $18, GDB_FR_FPR18(sp)
LDC1 $17, GDB_FR_FPR17(sp)
LDC1 $16, GDB_FR_FPR16(sp)
LDC1 $15, GDB_FR_FPR15(sp)
LDC1 $14, GDB_FR_FPR14(sp)
LDC1 $13, GDB_FR_FPR13(sp)
LDC1 $12, GDB_FR_FPR12(sp)
LDC1 $11, GDB_FR_FPR11(sp)
LDC1 $10, GDB_FR_FPR10(sp)
LDC1 $9, GDB_FR_FPR9(sp)
LDC1 $8, GDB_FR_FPR8(sp)
LDC1 $7, GDB_FR_FPR7(sp)
LDC1 $6, GDB_FR_FPR6(sp)
LDC1 $5, GDB_FR_FPR5(sp)
LDC1 $4, GDB_FR_FPR4(sp)
LDC1 $3, GDB_FR_FPR3(sp)
LDC1 $2, GDB_FR_FPR2(sp)
LDC1 $1, GDB_FR_FPR1(sp)
LDC1 $0, GDB_FR_FPR0(sp)
/*
* Now the CP0 and integer registers
*/
3:
#ifdef CONFIG_MIPS_MT_SMTC
/* Read-modify write of Status must be atomic */
mfc0 t2, CP0_TCSTATUS
ori t1, t2, TCSTATUS_IXMT
mtc0 t1, CP0_TCSTATUS
andi t2, t2, TCSTATUS_IXMT
_ehb
DMT 9 # dmt t1
jal mips_ihb
nop
#endif /* CONFIG_MIPS_MT_SMTC */
mfc0 t0, CP0_STATUS
ori t0, 0x1f
xori t0, 0x1f
mtc0 t0, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
andi t1, t1, VPECONTROL_TE
beqz t1, 9f
nop
EMT # emt
9:
mfc0 t1, CP0_TCSTATUS
xori t1, t1, TCSTATUS_IXMT
or t1, t1, t2
mtc0 t1, CP0_TCSTATUS
_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_L v0, GDB_FR_STATUS(sp)
LONG_L v1, GDB_FR_EPC(sp)
mtc0 v0, CP0_STATUS
DMTC0 v1, CP0_EPC
LONG_L v0, GDB_FR_HI(sp)
LONG_L v1, GDB_FR_LO(sp)
mthi v0
mtlo v1
LONG_L $31, GDB_FR_REG31(sp)
LONG_L $30, GDB_FR_REG30(sp)
LONG_L $28, GDB_FR_REG28(sp)
LONG_L $27, GDB_FR_REG27(sp)
LONG_L $26, GDB_FR_REG26(sp)
LONG_L $25, GDB_FR_REG25(sp)
LONG_L $24, GDB_FR_REG24(sp)
LONG_L $23, GDB_FR_REG23(sp)
LONG_L $22, GDB_FR_REG22(sp)
LONG_L $21, GDB_FR_REG21(sp)
LONG_L $20, GDB_FR_REG20(sp)
LONG_L $19, GDB_FR_REG19(sp)
LONG_L $18, GDB_FR_REG18(sp)
LONG_L $17, GDB_FR_REG17(sp)
LONG_L $16, GDB_FR_REG16(sp)
LONG_L $15, GDB_FR_REG15(sp)
LONG_L $14, GDB_FR_REG14(sp)
LONG_L $13, GDB_FR_REG13(sp)
LONG_L $12, GDB_FR_REG12(sp)
LONG_L $11, GDB_FR_REG11(sp)
LONG_L $10, GDB_FR_REG10(sp)
LONG_L $9, GDB_FR_REG9(sp)
LONG_L $8, GDB_FR_REG8(sp)
LONG_L $7, GDB_FR_REG7(sp)
LONG_L $6, GDB_FR_REG6(sp)
LONG_L $5, GDB_FR_REG5(sp)
LONG_L $4, GDB_FR_REG4(sp)
LONG_L $3, GDB_FR_REG3(sp)
LONG_L $2, GDB_FR_REG2(sp)
LONG_L $1, GDB_FR_REG1(sp)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
LONG_L k0, GDB_FR_EPC(sp)
LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */
jr k0
rfe
#else
LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */
.set mips3
eret
.set mips0
#endif
.set at
.set reorder
END(trap_low)
LEAF(kgdb_read_byte)
4: lb t0, (a0)
sb t0, (a1)
li v0, 0
jr ra
.section __ex_table,"a"
PTR 4b, kgdbfault
.previous
END(kgdb_read_byte)
LEAF(kgdb_write_byte)
5: sb a0, (a1)
li v0, 0
jr ra
.section __ex_table,"a"
PTR 5b, kgdbfault
.previous
END(kgdb_write_byte)
.type kgdbfault@function
.ent kgdbfault
kgdbfault: li v0, -EFAULT
jr ra
.end kgdbfault

1155
arch/mips/kernel/gdb-stub.c
View File

File diff suppressed because it is too large Load Diff

21
arch/mips/kernel/irq.c
View File

@ -126,19 +126,6 @@ asmlinkage void spurious_interrupt(void)
atomic_inc(&irq_err_count);
}
#ifdef CONFIG_KGDB
extern void breakpoint(void);
extern void set_debug_traps(void);
static int kgdb_flag = 1;
static int __init nokgdb(char *str)
{
kgdb_flag = 0;
return 1;
}
__setup("nokgdb", nokgdb);
#endif
void __init init_IRQ(void)
{
int i;
@ -147,12 +134,4 @@ void __init init_IRQ(void)
set_irq_noprobe(i);
arch_init_irq();
#ifdef CONFIG_KGDB
if (kgdb_flag) {
printk("Wait for gdb client connection ...\n");
set_debug_traps();
breakpoint();
}
#endif
}

1
arch/mips/mti-malta/Makefile
View File

@ -13,7 +13,6 @@ obj-y := malta-amon.o malta-cmdline.o \
obj-$(CONFIG_EARLY_PRINTK) += malta-console.o
obj-$(CONFIG_PCI) += malta-pci.o
obj-$(CONFIG_KGDB) += malta-kgdb.o
# FIXME FIXME FIXME
obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o

54
arch/mips/mti-malta/malta-init.c
View File

@ -37,15 +37,6 @@
#include <asm/mips-boards/malta.h>
#ifdef CONFIG_KGDB
extern int rs_kgdb_hook(int, int);
extern int rs_putDebugChar(char);
extern char rs_getDebugChar(void);
extern int saa9730_kgdb_hook(int);
extern int saa9730_putDebugChar(char);
extern char saa9730_getDebugChar(void);
#endif
int prom_argc;
int *_prom_argv, *_prom_envp;
@ -173,51 +164,6 @@ static void __init console_config(void)
}
#endif
#ifdef CONFIG_KGDB
void __init kgdb_config(void)
{
extern int (*generic_putDebugChar)(char);
extern char (*generic_getDebugChar)(void);
char *argptr;
int line, speed;
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
argptr += strlen("kgdb=ttyS");
if (*argptr != '0' && *argptr != '1')
printk("KGDB: Unknown serial line /dev/ttyS%c, "
"falling back to /dev/ttyS1\n", *argptr);
line = *argptr == '0' ? 0 : 1;
printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
speed = 0;
if (*++argptr == ',')
{
int c;
while ((c = *++argptr) && ('0' <= c && c <= '9'))
speed = speed * 10 + c - '0';
}
{
speed = rs_kgdb_hook(line, speed);
generic_putDebugChar = rs_putDebugChar;
generic_getDebugChar = rs_getDebugChar;
}
pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
"session, please connect your debugger\n",
line ? 1 : 0, speed);
{
char *s;
for (s = "Please connect GDB to this port\r\n"; *s; )
generic_putDebugChar(*s++);
}
/* Breakpoint is invoked after interrupts are initialised */
}
}
#endif
static void __init mips_nmi_setup(void)
{
void *base;

133
arch/mips/mti-malta/malta-kgdb.c
View File

@ -1,133 +0,0 @@
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* This is the interface to the remote debugger stub.
*/
#include <linux/types.h>
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
#include <asm/io.h>
static struct serial_state rs_table[] = {
SERIAL_PORT_DFNS /* Defined in serial.h */
};
static struct async_struct kdb_port_info = {0};
int (*generic_putDebugChar)(char);
char (*generic_getDebugChar)(void);
static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
{
return inb(info->port + offset);
}
static __inline__ void serial_out(struct async_struct *info, int offset,
int value)
{
outb(value, info->port+offset);
}
int rs_kgdb_hook(int tty_no, int speed) {
int t;
struct serial_state *ser = &rs_table[tty_no];
kdb_port_info.state = ser;
kdb_port_info.magic = SERIAL_MAGIC;
kdb_port_info.port = ser->port;
kdb_port_info.flags = ser->flags;
/*
* Clear all interrupts
*/
serial_in(&kdb_port_info, UART_LSR);
serial_in(&kdb_port_info, UART_RX);
serial_in(&kdb_port_info, UART_IIR);
serial_in(&kdb_port_info, UART_MSR);
/*
* Now, initialize the UART
*/
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
if (kdb_port_info.flags & ASYNC_FOURPORT) {
kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
t = UART_MCR_DTR | UART_MCR_OUT1;
} else {
kdb_port_info.MCR
= UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
t = UART_MCR_DTR | UART_MCR_RTS;
}
kdb_port_info.MCR = t; /* no interrupts, please */
serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
/*
* and set the speed of the serial port
*/
if (speed == 0)
speed = 9600;
t = kdb_port_info.state->baud_base / speed;
/* set DLAB */
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */
/* reset DLAB */
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
return speed;
}
int putDebugChar(char c)
{
return generic_putDebugChar(c);
}
char getDebugChar(void)
{
return generic_getDebugChar();
}
int rs_putDebugChar(char c)
{
if (!kdb_port_info.state) { /* need to init device first */
return 0;
}
while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
;
serial_out(&kdb_port_info, UART_TX, c);
return 1;
}
char rs_getDebugChar(void)
{
if (!kdb_port_info.state) { /* need to init device first */
return 0;
}
while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
;
return serial_in(&kdb_port_info, UART_RX);
}

4
arch/mips/mti-malta/malta-setup.c
View File

@ -199,10 +199,6 @@ void __init plat_mem_setup(void)
*/
enable_dma(4);
#ifdef CONFIG_KGDB
kgdb_config();
#endif
#ifdef CONFIG_DMA_COHERENT
if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
panic("Hardware DMA cache coherency not supported");

1
arch/mips/nxp/pnx8550/common/Makefile
View File

@ -24,6 +24,5 @@
obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += gdb_hook.o
EXTRA_CFLAGS += -Werror

109
arch/mips/nxp/pnx8550/common/gdb_hook.c
View File

@ -1,109 +0,0 @@
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* This is the interface to the remote debugger stub.
*
*/
#include <linux/types.h>
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <linux/serial_ip3106.h>
#include <asm/serial.h>
#include <asm/io.h>
#include <uart.h>
static struct serial_state rs_table[IP3106_NR_PORTS] = {
};
static struct async_struct kdb_port_info = {0};
void rs_kgdb_hook(int tty_no)
{
struct serial_state *ser = &rs_table[tty_no];
kdb_port_info.state = ser;
kdb_port_info.magic = SERIAL_MAGIC;
kdb_port_info.port = tty_no;
kdb_port_info.flags = ser->flags;
/*
* Clear all interrupts
*/
/* Clear all the transmitter FIFO counters (pointer and status) */
ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
/* Clear all the receiver FIFO counters (pointer and status) */
ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
/* Clear all interrupts */
ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
IP3106_UART_INT_ALLTX;
/*
* Now, initialize the UART
*/
ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
}
int putDebugChar(char c)
{
/* Wait until FIFO not full */
while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
;
/* Send one char */
ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
return 1;
}
char getDebugChar(void)
{
char ch;
/* Wait until there is a char in the FIFO */
while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
IP3106_UART_FIFO_RXFIFO) >> 8))
;
/* Read one char */
ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
IP3106_UART_FIFO_RBRTHR;
/* Advance the RX FIFO read pointer */
ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
return (ch);
}
void rs_disable_debug_interrupts(void)
{
ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
}
void rs_enable_debug_interrupts(void)
{
/* Clear all the transmitter FIFO counters (pointer and status) */
ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
/* Clear all the receiver FIFO counters (pointer and status) */
ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
/* Clear all interrupts */
ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
IP3106_UART_INT_ALLTX;
ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
}

1
arch/mips/nxp/pnx8550/common/int.c
View File

@ -34,7 +34,6 @@
#include <linux/module.h>
#include <asm/io.h>
#include <asm/gdb-stub.h>
#include <int.h>
#include <uart.h>

1
arch/mips/nxp/pnx8550/common/proc.c
View File

@ -22,7 +22,6 @@
#include <linux/random.h>
#include <asm/io.h>
#include <asm/gdb-stub.h>
#include <int.h>
#include <uart.h>

12
arch/mips/nxp/pnx8550/common/setup.c
View File

@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
extern void pnx8550_machine_power_off(void);
extern struct resource ioport_resource;
extern struct resource iomem_resource;
extern void rs_kgdb_hook(int tty_no);
extern char *prom_getcmdline(void);
struct resource standard_io_resources[] = {
@ -142,16 +141,5 @@ void __init plat_mem_setup(void)
ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
}
#ifdef CONFIG_KGDB
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
int line;
argptr += strlen("kgdb=ttyS");
line = *argptr == '0' ? 0 : 1;
rs_kgdb_hook(line);
pr_info("KGDB: Using ttyS%i for session, "
"please connect your debugger\n", line ? 1 : 0);
}
#endif
return;
}

73
arch/mips/pmc-sierra/msp71xx/msp_serial.c
View File

@ -38,68 +38,6 @@
#include <msp_int.h>
#include <msp_regs.h>
#ifdef CONFIG_KGDB
/*
* kgdb uses serial port 1 so the console can remain on port 0.
* To use port 0 change the definition to read as follows:
* #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
*/
#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
int putDebugChar(char c)
{
volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
uint32_t val = (uint32_t)c;
local_irq_disable();
while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
uart[0] = val;
while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
local_irq_enable();
return 1;
}
char getDebugChar(void)
{
volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
uint32_t val;
while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
val = uart[0];
return (char)val;
}
void initDebugPort(unsigned int uartclk, unsigned int baudrate)
{
unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
/* Enable FIFOs */
writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
(char *)DEBUG_PORT_BASE + (UART_FCR * 4));
/* Select brtc divisor */
writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
/* Store divisor lsb */
writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
/* Store divisor msb */
writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
/* Set 8N1 mode */
writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
/* Disable flow control */
writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
/* Disable receive interrupt(!) */
writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
}
#endif
void __init msp_serial_setup(void)
{
char *s;
@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
case MACH_MSP7120_FPGA:
/* Enable UART1 on MSP4200 and MSP7120 */
*GPIO_CFG2_REG = 0x00002299;
#ifdef CONFIG_KGDB
/* Initialize UART1 for kgdb since PMON doesn't */
if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
if( mips_machtype == MACH_MSP4200_FPGA
|| mips_machtype == MACH_MSP7120_FPGA )
initDebugPort(uartclk, 19200);
else
initDebugPort(uartclk, 57600);
}
#endif
break;
default:

1
arch/mips/pmc-sierra/yosemite/Makefile
View File

@ -4,7 +4,6 @@
obj-y += irq.o prom.o py-console.o setup.o
obj-$(CONFIG_KGDB) += dbg_io.o
obj-$(CONFIG_SMP) += smp.o
EXTRA_CFLAGS += -Werror

180
arch/mips/pmc-sierra/yosemite/dbg_io.c
View File

@ -1,180 +0,0 @@
/*
* Copyright 2003 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Support for KGDB for the Yosemite board. We make use of single serial
* port to be used for KGDB as well as console. The second serial port
* seems to be having a problem. Single IRQ is allocated for both the
* ports. Hence, the interrupt routing code needs to figure out whether
* the interrupt came from channel A or B.
*/
#include <asm/serial.h>
/*
* Baud rate, Parity, Data and Stop bit settings for the
* serial port on the Yosemite. Note that the Early printk
* patch has been added. So, we should be all set to go
*/
#define YOSEMITE_BAUD_2400 2400
#define YOSEMITE_BAUD_4800 4800
#define YOSEMITE_BAUD_9600 9600
#define YOSEMITE_BAUD_19200 19200
#define YOSEMITE_BAUD_38400 38400
#define YOSEMITE_BAUD_57600 57600
#define YOSEMITE_BAUD_115200 115200
#define YOSEMITE_PARITY_NONE 0
#define YOSEMITE_PARITY_ODD 0x08
#define YOSEMITE_PARITY_EVEN 0x18
#define YOSEMITE_PARITY_MARK 0x28
#define YOSEMITE_PARITY_SPACE 0x38
#define YOSEMITE_DATA_5BIT 0x0
#define YOSEMITE_DATA_6BIT 0x1
#define YOSEMITE_DATA_7BIT 0x2
#define YOSEMITE_DATA_8BIT 0x3
#define YOSEMITE_STOP_1BIT 0x0
#define YOSEMITE_STOP_2BIT 0x4
/* This is crucial */
#define SERIAL_REG_OFS 0x1
#define SERIAL_RCV_BUFFER 0x0
#define SERIAL_TRANS_HOLD 0x0
#define SERIAL_SEND_BUFFER 0x0
#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS)
#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS)
#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS)
#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS)
#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS)
#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS)
#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS)
#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS)
#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS)
#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS)
#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS)
#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS)
/*
* Functions to READ and WRITE to serial port 0
*/
#define SERIAL_READ(ofs) (*((volatile unsigned char*) \
(TITAN_SERIAL_BASE + ofs)))
#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \
(TITAN_SERIAL_BASE + ofs))) = val)
/*
* Functions to READ and WRITE to serial port 1
*/
#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs)))
#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs))) = val)
/*
* Second serial port initialization
*/
void init_second_port(void)
{
/* Disable Interrupts */
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
{
unsigned int divisor;
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
(divisor & 0xff00) >> 8);
SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
}
SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
/* Enable Interrupts */
SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
}
/* Initialize the serial port for KGDB debugging */
void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
unsigned char stop)
{
/* Disable Interrupts */
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
{
unsigned int divisor;
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
divisor = TITAN_SERIAL_BASE_BAUD / baud;
SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
}
SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
unsigned char getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(YOSEMITE_BAUD_115200,
YOSEMITE_DATA_8BIT,
YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
}
while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
return SERIAL_READ(SERIAL_RCV_BUFFER);
}
int putDebugChar(unsigned char byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(YOSEMITE_BAUD_115200,
YOSEMITE_DATA_8BIT,
YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
}
while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
return 1;
}

9
arch/mips/pmc-sierra/yosemite/irq.c
View File

@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
}
}
#ifdef CONFIG_KGDB
extern void init_second_port(void);
#endif
/*
* Initialize the next level interrupt handler
*/
@ -156,11 +152,6 @@ void __init arch_init_irq(void)
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
#ifdef CONFIG_KGDB
/* At this point, initialize the second serial port */
init_second_port();
#endif
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif

25
arch/mips/sgi-ip22/ip22-setup.c
View File

@ -20,7 +20,6 @@
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/gdb-stub.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/sgialib.h>
@ -81,30 +80,6 @@ void __init plat_mem_setup(void)
add_preferred_console("arc", 0, NULL);
}
#ifdef CONFIG_KGDB
{
char *kgdb_ttyd = prom_getcmdline();
if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
int line;
kgdb_ttyd += strlen("kgdb=ttyd");
if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c"
", falling back to /dev/ttyd1\n", *kgdb_ttyd);
line = *kgdb_ttyd == '2' ? 0 : 1;
printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
"session\n", line ? 1 : 2);
rs_kgdb_hook(line);
printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
"session, please connect your debugger\n", line ? 1:2);
kgdb_enabled = 1;
/* Breakpoints and stuff are in sgi_irq_setup() */
}
}
#endif
#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
{
ULONG *gfxinfo;

1
arch/mips/sgi-ip27/Makefile
View File

@ -7,7 +7,6 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
ip27-xtalk.o
obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
obj-$(CONFIG_KGDB) += ip27-dbgio.o
obj-$(CONFIG_SMP) += ip27-smp.o
EXTRA_CFLAGS += -Werror

60
arch/mips/sgi-ip27/ip27-dbgio.c
View File

@ -1,60 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
*/
#include <asm/sn/addrs.h>
#include <asm/sn/sn0/hub.h>
#include <asm/sn/klconfig.h>
#include <asm/sn/ioc3.h>
#include <asm/sn/sn_private.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#define IOC3_CLK (22000000 / 3)
#define IOC3_FLAGS (0)
static inline struct ioc3_uartregs *console_uart(void)
{
struct ioc3 *ioc3;
ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base;
return &ioc3->sregs.uarta;
}
unsigned char getDebugChar(void)
{
struct ioc3_uartregs *uart = console_uart();
while ((uart->iu_lsr & UART_LSR_DR) == 0);
return uart->iu_rbr;
}
void putDebugChar(unsigned char c)
{
struct ioc3_uartregs *uart = console_uart();
while ((uart->iu_lsr & UART_LSR_THRE) == 0);
uart->iu_thr = c;
}

80
arch/mips/sibyte/bcm1480/irq.c
View File

@ -57,30 +57,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
extern unsigned long ht_eoi_space;
#endif
#ifdef CONFIG_KGDB
#include <asm/gdb-stub.h>
extern void breakpoint(void);
static int kgdb_irq;
#ifdef CONFIG_GDB_CONSOLE
extern void register_gdb_console(void);
#endif
/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
static int kgdb_flag = 1;
static int __init nokgdb(char *str)
{
kgdb_flag = 0;
return 1;
}
__setup("nokgdb", nokgdb);
/* Default to UART1 */
int kgdb_port = 1;
#ifdef CONFIG_SERIAL_SB1250_DUART
extern char sb1250_duart_present[];
#endif
#endif
static struct irq_chip bcm1480_irq_type = {
.name = "BCM1480-IMR",
.ack = ack_bcm1480_irq,
@ -355,61 +331,10 @@ void __init arch_init_irq(void)
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SERIAL_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
/* QQQ FIXME */
__raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
__raw_writeq(IMR_IP6_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(kgdb_irq << 3)));
bcm1480_unmask_irq(0, kgdb_irq);
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif
printk("Waiting for GDB on UART port %d\n", kgdb_port);
set_debug_traps();
breakpoint();
}
#endif
}
#ifdef CONFIG_KGDB
#include <linux/delay.h>
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
static void bcm1480_kgdb_interrupt(void)
{
/*
* Clear break-change status (allow some time for the remote
* host to stop the break, since we would see another
* interrupt on the end-of-break too)
*/
kstat.irqs[smp_processor_id()][kgdb_irq]++;
mdelay(500);
duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
M_DUART_RX_EN | M_DUART_TX_EN);
set_async_breakpoint(&get_irq_regs()->cp0_epc);
}
#endif /* CONFIG_KGDB */
extern void bcm1480_mailbox_interrupt(void);
static inline void dispatch_ip2(void)
@ -462,11 +387,6 @@ asmlinkage void plat_irq_dispatch(void)
bcm1480_mailbox_interrupt();
#endif
#ifdef CONFIG_KGDB
else if (pending & CAUSEF_IP6)
bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
#endif
else if (pending & CAUSEF_IP2)
dispatch_ip2();
}

14
arch/mips/sibyte/cfe/setup.c
View File

@ -59,10 +59,6 @@ int cfe_cons_handle;
extern unsigned long initrd_start, initrd_end;
#endif
#ifdef CONFIG_KGDB
extern int kgdb_port;
#endif
static void __noreturn cfe_linux_exit(void *arg)
{
int warm = *(int *)arg;
@ -246,9 +242,6 @@ void __init prom_init(void)
int argc = fw_arg0;
char **envp = (char **) fw_arg2;
int *prom_vec = (int *) fw_arg3;
#ifdef CONFIG_KGDB
char *arg;
#endif
_machine_restart = cfe_linux_restart;
_machine_halt = cfe_linux_halt;
@ -309,13 +302,6 @@ void __init prom_init(void)
}
}
#ifdef CONFIG_KGDB
if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
kgdb_port = (arg[10] == '0') ? 0 : 1;
else
kgdb_port = 1;
#endif
#ifdef CONFIG_BLK_DEV_INITRD
{
char *ptr;

60
arch/mips/sibyte/sb1250/irq.c
View File

@ -57,16 +57,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
extern unsigned long ldt_eoi_space;
#endif
#ifdef CONFIG_KGDB
static int kgdb_irq;
/* Default to UART1 */
int kgdb_port = 1;
#ifdef CONFIG_SERIAL_SB1250_DUART
extern char sb1250_duart_present[];
#endif
#endif
static struct irq_chip sb1250_irq_type = {
.name = "SB1250-IMR",
.ack = ack_sb1250_irq,
@ -313,55 +303,10 @@ void __init arch_init_irq(void)
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SERIAL_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
__raw_writeq(M_DUART_IMR_BRK,
IOADDR(A_DUART_IMRREG(kgdb_port)));
__raw_writeq(IMR_IP6_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(kgdb_irq << 3)));
sb1250_unmask_irq(0, kgdb_irq);
}
#endif
}
#ifdef CONFIG_KGDB
#include <linux/delay.h>
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
static void sb1250_kgdb_interrupt(void)
{
/*
* Clear break-change status (allow some time for the remote
* host to stop the break, since we would see another
* interrupt on the end-of-break too)
*/
kstat_this_cpu.irqs[kgdb_irq]++;
mdelay(500);
duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
M_DUART_RX_EN | M_DUART_TX_EN);
set_async_breakpoint(&get_irq_regs()->cp0_epc);
}
#endif /* CONFIG_KGDB */
extern void sb1250_mailbox_interrupt(void);
static inline void dispatch_ip2(void)
@ -407,11 +352,6 @@ asmlinkage void plat_irq_dispatch(void)
sb1250_mailbox_interrupt();
#endif
#ifdef CONFIG_KGDB
else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
sb1250_kgdb_interrupt();
#endif
else if (pending & CAUSEF_IP2)
dispatch_ip2();
else

1
arch/mips/sibyte/swarm/Makefile
View File

@ -1,4 +1,3 @@
obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o
obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o
obj-$(CONFIG_KGDB) += dbg_io.o

76
arch/mips/sibyte/swarm/dbg_io.c
View File

@ -1,76 +0,0 @@
/*
* kgdb debug routines for SiByte boards.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/* -------------------- BEGINNING OF CONFIG --------------------- */
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/addrspace.h>
/*
* We use the second serial port for kgdb traffic.
* 115200, 8, N, 1.
*/
#define BAUD_RATE 115200
#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE)
#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */
#define PARITY V_DUART_PARITY_MODE_NONE /* or even */
#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */
static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
/* -------------------- END OF CONFIG --------------------- */
extern int kgdb_port;
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
void putDebugChar(unsigned char c);
unsigned char getDebugChar(void);
static void
duart_init(int clk_divisor, int data, int parity, int stop)
{
duart_out(R_DUART_MODE_REG_1, data | parity);
duart_out(R_DUART_MODE_REG_2, stop);
duart_out(R_DUART_CLK_SEL, clk_divisor);
duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */
}
void
putDebugChar(unsigned char c)
{
if (!duart_initialized) {
duart_initialized = 1;
duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
}
while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
duart_out(R_DUART_TX_HOLD, c);
}
unsigned char
getDebugChar(void)
{
if (!duart_initialized) {
duart_initialized = 1;
duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
}
while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
return duart_in(R_DUART_RX_HOLD);
}

2
arch/mips/txx9/Kconfig
View File

@ -60,7 +60,6 @@ config SOC_TX4927
select HW_HAS_PCI
select IRQ_TXX9
select PCI_TX4927
select SYS_SUPPORTS_KGDB
select GPIO_TXX9
config SOC_TX4938
@ -70,7 +69,6 @@ config SOC_TX4938
select HW_HAS_PCI
select IRQ_TXX9
select PCI_TX4927
select SYS_SUPPORTS_KGDB
select GPIO_TXX9
config TOSHIBA_FPCIB0

1
arch/mips/txx9/generic/Makefile
View File

@ -8,6 +8,5 @@ obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
obj-$(CONFIG_KGDB) += dbgio.o
EXTRA_CFLAGS += -Werror

48
arch/mips/txx9/generic/dbgio.c
View File

@ -1,48 +0,0 @@
/*
* linux/arch/mips/tx4938/common/dbgio.c
*
* kgdb interface for gdb
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
*/
#include <linux/types>
extern u8 txx9_sio_kdbg_rd(void);
extern int txx9_sio_kdbg_wr( u8 ch );
u8 getDebugChar(void)
{
return (txx9_sio_kdbg_rd());
}
int putDebugChar(u8 byte)
{
return (txx9_sio_kdbg_wr(byte));
}

1
arch/mips/txx9/jmr3927/Makefile
View File

@ -3,6 +3,5 @@
#
obj-y += prom.o irq.o setup.o
obj-$(CONFIG_KGDB) += kgdb_io.o
EXTRA_CFLAGS += -Werror

105
arch/mips/txx9/jmr3927/kgdb_io.c
View File

@ -1,105 +0,0 @@
/*
* BRIEF MODULE DESCRIPTION
* Low level uart routines to directly access a TX[34]927 SIO.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com or source@mvista.com
*
* Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/txx9/jmr3927.h>
#define TIMEOUT 0xffffff
static int remoteDebugInitialized = 0;
static void debugInit(int baud);
int putDebugChar(unsigned char c)
{
int i = 0;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(38400);
}
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(0)->tfifo = c;
return 1;
}
unsigned char getDebugChar(void)
{
int i = 0;
int dicr;
char c;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(38400);
}
/* diable RX int. */
dicr = tx3927_sioptr(0)->dicr;
tx3927_sioptr(0)->dicr = 0;
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
;
c = tx3927_sioptr(0)->rfifo;
/* clear RX int. status */
tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
/* enable RX int. */
tx3927_sioptr(0)->dicr = dicr;
return c;
}
static void debugInit(int baud)
{
tx3927_sioptr(0)->lcr = 0x020;
tx3927_sioptr(0)->dicr = 0;
tx3927_sioptr(0)->disr = 0x4100;
tx3927_sioptr(0)->cisr = 0x014;
tx3927_sioptr(0)->fcr = 0;
tx3927_sioptr(0)->flcr = 0x02;
tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
TXx927_SIBGR_BCLK_T0;
}

215
include/asm-mips/gdb-stub.h
View File

@ -1,215 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 Andreas Busse
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef _ASM_GDB_STUB_H
#define _ASM_GDB_STUB_H
/*
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
/*
* Saved floating point registers
*/
#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
/*
* Again, CP0 registers
*/
#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
#ifndef __ASSEMBLY__
/*
* This is the same as above, but for the high-level
* part of the GDB stub.
*/
struct gdb_regs {
/*
* Pad bytes for argument save space on the stack
* 24/48 Bytes for 32/64 bit code
*/
unsigned long pad0[6];
/*
* saved main processor registers
*/
long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15;
long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
/*
* Saved special registers
*/
long cp0_status;
long lo;
long hi;
long cp0_badvaddr;
long cp0_cause;
long cp0_epc;
/*
* Saved floating point registers
*/
long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
long cp1_fsr;
long cp1_fir;
/*
* Frame pointer
*/
long frame_ptr;
long dummy; /* unused */
/*
* saved cp0 registers
*/
long cp0_index;
long cp0_random;
long cp0_entrylo0;
long cp0_entrylo1;
long cp0_context;
long cp0_pagemask;
long cp0_wired;
long cp0_reg7;
long cp0_reg8;
long cp0_reg9;
long cp0_entryhi;
long cp0_reg11;
long cp0_reg12;
long cp0_reg13;
long cp0_reg14;
long cp0_prid;
};
/*
* Prototypes
*/
extern int kgdb_enabled;
void set_debug_traps(void);
void set_async_breakpoint(unsigned long *epc);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_GDB_STUB_H */