From f81dadbcf7fd067baf184b63c179fc392bdb226e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Thu, 9 May 2019 00:51:15 +0300 Subject: [PATCH 1/2] net: phy: realtek: Add rtl8211e rx/tx delays config There are two chip pins named TXDLY and RXDLY which actually adds the 2ns delays to TXC and RXC for TXD/RXD latching. Alas this is the only documented info regarding the RGMII timing control configurations the PHY provides. It turns out the same settings can be setup via MDIO registers hidden in the extension pages layout. Particularly the extension page 0xa4 provides a register 0x1c, which bits 1 and 2 control the described delays. They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. The hidden RGMII configs register utilization was found in the rtl8211e U-boot driver: https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 There is also a freebsd-folks discussion regarding this register: https://reviews.freebsd.org/D13591 It confirms that the register bits field must control the so called configuration pins described in the table 12-13 of the official PHY datasheet: 8:6 = PHY Address 5:4 = Auto-Negotiation 3 = Interface Mode Select 2 = RX Delay 1 = TX Delay 0 = SELRGV Reviewed-by: Andrew Lunn Signed-off-by: Serge Semin Signed-off-by: David S. Miller --- drivers/net/phy/realtek.c | 51 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index d6a10f323117..cfbc0ca61123 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -23,11 +23,15 @@ #define RTL821x_INSR 0x13 +#define RTL821x_EXT_PAGE_SELECT 0x1e #define RTL821x_PAGE_SELECT 0x1f #define RTL8211F_INSR 0x1d #define RTL8211F_TX_DELAY BIT(8) +#define RTL8211E_TX_DELAY BIT(1) +#define RTL8211E_RX_DELAY BIT(2) +#define RTL8211E_MODE_MII_GMII BIT(3) #define RTL8201F_ISR 0x1e #define RTL8201F_IER 0x13 @@ -167,6 +171,52 @@ static int rtl8211f_config_init(struct phy_device *phydev) return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); } +static int rtl8211e_config_init(struct phy_device *phydev) +{ + int ret = 0, oldpage; + u16 val; + + /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + val = 0; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + val = RTL8211E_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + val = RTL8211E_TX_DELAY; + break; + default: /* the rest of the modes imply leaving delays as is. */ + return 0; + } + + /* According to a sample driver there is a 0x1c config register on the + * 0xa4 extension page (0x7) layout. It can be used to disable/enable + * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can + * also be used to customize the whole configuration register: + * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select, + * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet + * for details). + */ + oldpage = phy_select_page(phydev, 0x7); + if (oldpage < 0) + goto err_restore_page; + + ret = phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); + if (ret) + goto err_restore_page; + + ret = phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, + val); + +err_restore_page: + return phy_restore_page(phydev, oldpage, ret); +} + static int rtl8211b_suspend(struct phy_device *phydev) { phy_write(phydev, MII_MMD_DATA, BIT(9)); @@ -239,6 +289,7 @@ static struct phy_driver realtek_drvs[] = { }, { PHY_ID_MATCH_EXACT(0x001cc915), .name = "RTL8211E Gigabit Ethernet", + .config_init = &rtl8211e_config_init, .ack_interrupt = &rtl821x_ack_interrupt, .config_intr = &rtl8211e_config_intr, .suspend = genphy_suspend, From 1da7756e6616c7795c8a104fde0a66f212ef659d Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Thu, 9 May 2019 00:51:17 +0300 Subject: [PATCH 2/2] net: phy: realtek: Change TX-delay setting for RGMII modes only It's prone to problems if delay is cleared out for other than RGMII modes. So lets set/clear the TX-delay in the config register only if actually RGMII-like interface mode is requested. This only concerns rtl8211f chips. Signed-off-by: Serge Semin Signed-off-by: David S. Miller --- drivers/net/phy/realtek.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index cfbc0ca61123..761ce3b1e7bd 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -161,12 +161,23 @@ static int rtl8211c_config_init(struct phy_device *phydev) static int rtl8211f_config_init(struct phy_device *phydev) { - u16 val = 0; + u16 val; - /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + /* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and + * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin. + */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + val = 0; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: val = RTL8211F_TX_DELAY; + break; + default: /* the rest of the modes imply leaving delay as is. */ + return 0; + } return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); }