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drm/amd/display: Prefix TIMING_STANDARD entries with DC_ 

Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Reza Amini 2018-05-09 15:41:47 -04:00 committed by Alex Deucher
parent e0d4234982
commit 8de94233f4
5 changed files with 35 additions and 28 deletions
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2
drivers/gpu/drm/amd/display/dc/core/dc.c
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@ -1564,7 +1564,7 @@ struct dc_sink *dc_link_add_remote_sink(
struct dc_sink *dc_sink;
enum dc_edid_status edid_status;
if (len > MAX_EDID_BUFFER_SIZE) {
if (len > DC_MAX_EDID_BUFFER_SIZE) {
dm_error("Max EDID buffer size breached!\n");
return NULL;
}

2
drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
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@ -109,7 +109,7 @@ struct ddc_service {
uint32_t address;
uint32_t edid_buf_len;
uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
};
#endif /* DC_DDC_TYPES_H_ */

34
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -567,25 +567,25 @@ struct scaling_taps {
};
enum dc_timing_standard {
TIMING_STANDARD_UNDEFINED,
TIMING_STANDARD_DMT,
TIMING_STANDARD_GTF,
TIMING_STANDARD_CVT,
TIMING_STANDARD_CVT_RB,
TIMING_STANDARD_CEA770,
TIMING_STANDARD_CEA861,
TIMING_STANDARD_HDMI,
TIMING_STANDARD_TV_NTSC,
TIMING_STANDARD_TV_NTSC_J,
TIMING_STANDARD_TV_PAL,
TIMING_STANDARD_TV_PAL_M,
TIMING_STANDARD_TV_PAL_CN,
TIMING_STANDARD_TV_SECAM,
TIMING_STANDARD_EXPLICIT,
DC_TIMING_STANDARD_UNDEFINED,
DC_TIMING_STANDARD_DMT,
DC_TIMING_STANDARD_GTF,
DC_TIMING_STANDARD_CVT,
DC_TIMING_STANDARD_CVT_RB,
DC_TIMING_STANDARD_CEA770,
DC_TIMING_STANDARD_CEA861,
DC_TIMING_STANDARD_HDMI,
DC_TIMING_STANDARD_TV_NTSC,
DC_TIMING_STANDARD_TV_NTSC_J,
DC_TIMING_STANDARD_TV_PAL,
DC_TIMING_STANDARD_TV_PAL_M,
DC_TIMING_STANDARD_TV_PAL_CN,
DC_TIMING_STANDARD_TV_SECAM,
DC_TIMING_STANDARD_EXPLICIT,
/*!< For explicit timings from EDID, VBIOS, etc.*/
TIMING_STANDARD_USER_OVERRIDE,
DC_TIMING_STANDARD_USER_OVERRIDE,
/*!< For mode timing override by user*/
TIMING_STANDARD_MAX
DC_TIMING_STANDARD_MAX
};
enum dc_color_depth {

18
drivers/gpu/drm/amd/display/dc/dc_types.h
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@ -98,7 +98,7 @@ struct dc_context {
};
#define MAX_EDID_BUFFER_SIZE 512
#define DC_MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
#define MAX_SURFACE_NUM 4
#define NUM_PIXEL_FORMATS 10
@ -137,13 +137,13 @@ enum plane_stereo_format {
*/
enum dc_edid_connector_type {
EDID_CONNECTOR_UNKNOWN = 0,
EDID_CONNECTOR_ANALOG = 1,
EDID_CONNECTOR_DIGITAL = 10,
EDID_CONNECTOR_DVI = 11,
EDID_CONNECTOR_HDMIA = 12,
EDID_CONNECTOR_MDDI = 14,
EDID_CONNECTOR_DISPLAYPORT = 15
DC_EDID_CONNECTOR_UNKNOWN = 0,
DC_EDID_CONNECTOR_ANALOG = 1,
DC_EDID_CONNECTOR_DIGITAL = 10,
DC_EDID_CONNECTOR_DVI = 11,
DC_EDID_CONNECTOR_HDMIA = 12,
DC_EDID_CONNECTOR_MDDI = 14,
DC_EDID_CONNECTOR_DISPLAYPORT = 15
};
enum dc_edid_status {
@ -169,7 +169,7 @@ struct dc_cea_audio_mode {
struct dc_edid {
uint32_t length;
uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
};
/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION

7
drivers/gpu/drm/amd/display/include/fixed31_32.h
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@ -26,6 +26,13 @@
#ifndef __DAL_FIXED31_32_H__
#define __DAL_FIXED31_32_H__
#ifndef LLONG_MAX
#define LLONG_MAX 9223372036854775807ll
#endif
#ifndef LLONG_MIN
#define LLONG_MIN (-LLONG_MAX - 1ll)
#endif
#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
#ifndef LLONG_MIN
#define LLONG_MIN (1LL<<63)