drm/amd/display: Prefix TIMING_STANDARD entries with DC_
Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1564,7 +1564,7 @@ struct dc_sink *dc_link_add_remote_sink(
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struct dc_sink *dc_sink;
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struct dc_sink *dc_sink;
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enum dc_edid_status edid_status;
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enum dc_edid_status edid_status;
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if (len > MAX_EDID_BUFFER_SIZE) {
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if (len > DC_MAX_EDID_BUFFER_SIZE) {
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dm_error("Max EDID buffer size breached!\n");
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dm_error("Max EDID buffer size breached!\n");
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return NULL;
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return NULL;
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}
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}
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@ -109,7 +109,7 @@ struct ddc_service {
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uint32_t address;
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uint32_t address;
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uint32_t edid_buf_len;
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uint32_t edid_buf_len;
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uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
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uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
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};
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};
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#endif /* DC_DDC_TYPES_H_ */
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#endif /* DC_DDC_TYPES_H_ */
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@ -567,25 +567,25 @@ struct scaling_taps {
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};
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};
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enum dc_timing_standard {
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enum dc_timing_standard {
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TIMING_STANDARD_UNDEFINED,
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DC_TIMING_STANDARD_UNDEFINED,
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TIMING_STANDARD_DMT,
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DC_TIMING_STANDARD_DMT,
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TIMING_STANDARD_GTF,
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DC_TIMING_STANDARD_GTF,
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TIMING_STANDARD_CVT,
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DC_TIMING_STANDARD_CVT,
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TIMING_STANDARD_CVT_RB,
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DC_TIMING_STANDARD_CVT_RB,
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TIMING_STANDARD_CEA770,
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DC_TIMING_STANDARD_CEA770,
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TIMING_STANDARD_CEA861,
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DC_TIMING_STANDARD_CEA861,
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TIMING_STANDARD_HDMI,
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DC_TIMING_STANDARD_HDMI,
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TIMING_STANDARD_TV_NTSC,
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DC_TIMING_STANDARD_TV_NTSC,
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TIMING_STANDARD_TV_NTSC_J,
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DC_TIMING_STANDARD_TV_NTSC_J,
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TIMING_STANDARD_TV_PAL,
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DC_TIMING_STANDARD_TV_PAL,
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TIMING_STANDARD_TV_PAL_M,
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DC_TIMING_STANDARD_TV_PAL_M,
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TIMING_STANDARD_TV_PAL_CN,
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DC_TIMING_STANDARD_TV_PAL_CN,
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TIMING_STANDARD_TV_SECAM,
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DC_TIMING_STANDARD_TV_SECAM,
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TIMING_STANDARD_EXPLICIT,
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DC_TIMING_STANDARD_EXPLICIT,
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/*!< For explicit timings from EDID, VBIOS, etc.*/
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/*!< For explicit timings from EDID, VBIOS, etc.*/
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TIMING_STANDARD_USER_OVERRIDE,
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DC_TIMING_STANDARD_USER_OVERRIDE,
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/*!< For mode timing override by user*/
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/*!< For mode timing override by user*/
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TIMING_STANDARD_MAX
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DC_TIMING_STANDARD_MAX
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};
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};
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enum dc_color_depth {
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enum dc_color_depth {
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@ -98,7 +98,7 @@ struct dc_context {
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};
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};
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#define MAX_EDID_BUFFER_SIZE 512
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#define DC_MAX_EDID_BUFFER_SIZE 512
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#define EDID_BLOCK_SIZE 128
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#define EDID_BLOCK_SIZE 128
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#define MAX_SURFACE_NUM 4
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#define MAX_SURFACE_NUM 4
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#define NUM_PIXEL_FORMATS 10
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#define NUM_PIXEL_FORMATS 10
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@ -137,13 +137,13 @@ enum plane_stereo_format {
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*/
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*/
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enum dc_edid_connector_type {
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enum dc_edid_connector_type {
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EDID_CONNECTOR_UNKNOWN = 0,
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DC_EDID_CONNECTOR_UNKNOWN = 0,
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EDID_CONNECTOR_ANALOG = 1,
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DC_EDID_CONNECTOR_ANALOG = 1,
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EDID_CONNECTOR_DIGITAL = 10,
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DC_EDID_CONNECTOR_DIGITAL = 10,
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EDID_CONNECTOR_DVI = 11,
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DC_EDID_CONNECTOR_DVI = 11,
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EDID_CONNECTOR_HDMIA = 12,
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DC_EDID_CONNECTOR_HDMIA = 12,
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EDID_CONNECTOR_MDDI = 14,
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DC_EDID_CONNECTOR_MDDI = 14,
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EDID_CONNECTOR_DISPLAYPORT = 15
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DC_EDID_CONNECTOR_DISPLAYPORT = 15
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};
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};
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enum dc_edid_status {
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enum dc_edid_status {
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@ -169,7 +169,7 @@ struct dc_cea_audio_mode {
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struct dc_edid {
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struct dc_edid {
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uint32_t length;
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uint32_t length;
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uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
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uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
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};
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};
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/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
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/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
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@ -26,6 +26,13 @@
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#ifndef __DAL_FIXED31_32_H__
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#ifndef __DAL_FIXED31_32_H__
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#define __DAL_FIXED31_32_H__
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#define __DAL_FIXED31_32_H__
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#ifndef LLONG_MAX
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#define LLONG_MAX 9223372036854775807ll
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#endif
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#ifndef LLONG_MIN
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#define LLONG_MIN (-LLONG_MAX - 1ll)
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#endif
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#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
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#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
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#ifndef LLONG_MIN
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#ifndef LLONG_MIN
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#define LLONG_MIN (1LL<<63)
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#define LLONG_MIN (1LL<<63)
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