powerpc/pmac: Simplify old pmac PIC interrupt handling
In the old days, we treated all interrupts from the legacy Apple home made interrupt controllers as level, with a trick reading the "level" register along with the "event" register to work arounds bugs where it would occasionally fail to latch some events. Doing so appeared to work fine for both level and edge interrupts. Later on, we discovered in Darwin source the magic masks that define which interrupts are actually level and which are edge, and implemented a different algorithm, more similar to what Apple does, that treats those differently. I recently discovered however that this caused problems (including loss of interrupts) with an old Wallstreet PowerBook when trying to use the internal modem (connected to a cascaded controller). It looks like some interrupts are treated as edge while they are really level and I'm starting to seriously doubt the correctness of the Darwin code (which has other obvious bugs when you read it, so ...) This patch reverts to our original behaviour of treating everything as a level interrupt. It appears to solve the problems with the modem on the Wallstreet and everything else seems to be working properly as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -52,13 +52,8 @@ struct device_node *of_irq_dflt_pic;
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/* Default addresses */
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static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
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#define GC_LEVEL_MASK 0x3ff00000
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#define OHARE_LEVEL_MASK 0x1ff00000
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#define HEATHROW_LEVEL_MASK 0x1ff00000
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static int max_irqs;
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static int max_real_irqs;
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static u32 level_mask[4];
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static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
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@ -217,8 +212,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
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for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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/* We must read level interrupts from the level register */
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bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
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bits |= in_le32(&pmac_irq_hw[i]->level);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
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continue;
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@ -248,8 +242,7 @@ static unsigned int pmac_pic_get_irq(void)
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for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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/* We must read level interrupts from the level register */
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bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
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bits |= in_le32(&pmac_irq_hw[i]->level);
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bits &= ppc_cached_irq_mask[i];
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if (bits == 0)
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continue;
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@ -284,19 +277,14 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
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static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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int level;
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if (hw >= max_irqs)
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return -EINVAL;
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/* Mark level interrupts, set delayed disable for edge ones and set
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* handlers
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*/
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level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
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if (level)
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &pmac_pic,
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level ? handle_level_irq : handle_edge_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
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return 0;
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}
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@ -334,21 +322,14 @@ static void __init pmac_pic_probe_oldstyle(void)
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if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
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max_irqs = max_real_irqs = 32;
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level_mask[0] = GC_LEVEL_MASK;
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} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
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max_irqs = max_real_irqs = 32;
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level_mask[0] = OHARE_LEVEL_MASK;
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/* We might have a second cascaded ohare */
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slave = of_find_node_by_name(NULL, "pci106b,7");
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if (slave) {
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if (slave)
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max_irqs = 64;
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level_mask[1] = OHARE_LEVEL_MASK;
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}
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} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
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max_irqs = max_real_irqs = 64;
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level_mask[0] = HEATHROW_LEVEL_MASK;
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level_mask[1] = 0;
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/* We might have a second cascaded heathrow */
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slave = of_find_node_by_name(master, "mac-io");
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@ -363,11 +344,8 @@ static void __init pmac_pic_probe_oldstyle(void)
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}
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/* We found a slave */
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if (slave) {
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if (slave)
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max_irqs = 128;
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level_mask[2] = HEATHROW_LEVEL_MASK;
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level_mask[3] = 0;
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}
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}
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BUG_ON(master == NULL);
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