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dmaengine: qcom_hidma: correct channel QOS register offset 

A regression was found while testing QOS with different channels.
The QOS register offset is 0x700 rather than 0x300.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
hifive-unleashed-5.1
Sinan Kaya 2017-07-16 10:30:38 -04:00 committed by Vinod Koul
parent 0217cccdbf
commit 8e7341750b
1 changed files with 1 additions and 1 deletions
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2
drivers/dma/qcom/hidma_mgmt.c
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@ -28,7 +28,7 @@
#include "hidma_mgmt.h"
#define HIDMA_QOS_N_OFFSET 0x300
#define HIDMA_QOS_N_OFFSET 0x700
#define HIDMA_CFG_OFFSET 0x400
#define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C
#define HIDMA_MAX_XACTIONS_OFFSET 0x420