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drm/imx: sec-dsim_imx: a general way to compute PLL PMS 

A fixed PLL PMS setting for attached panel is obviously not
enough for any other mipi panel which needs a different PLL
output clock frequency, and besides, for the CEA-861 standard
display modes, the 'pll_pms' table also can not cover all the
modes requirements. So a general way is created to solve this
problem which can provide an optimum solution to output a PLL
bit clock to match the request frequency in a maximum degree
and also satisfy the input clock and intermediate clocks limit
according to the PLL specification.

(This is the DSIM controller driver change for PLL PMS compute.)

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Fancy Fang 2019-03-17 12:16:26 +08:00 committed by Dong Aisheng
parent 4d9cab94fb
commit 8e76a569c4
2 changed files with 52 additions and 1 deletions
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4
drivers/gpu/drm/imx/sec_mipi_dsim-imx.c
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@ -1,7 +1,7 @@
/*
* Samsung MIPI DSI Host Controller on IMX
*
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -32,6 +32,7 @@
#include "imx-drm.h"
#include "sec_mipi_dphy_ln14lpp.h"
#include "sec_mipi_pll_1432x.h"
#define DRIVER_NAME "imx_sec_dsim_drv"
@ -197,6 +198,7 @@ static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
.version = 0x1060200,
.max_data_lanes = 4,
.max_data_rate = 1500000000ULL,
.dphy_pll = &pll_1432x,
.dphy_timing = dphy_timing_ln14lpp_v1p2,
.num_dphy_timing = ARRAY_SIZE(dphy_timing_ln14lpp_v1p2),
.dphy_timing_cmp = dphy_timing_default_cmp,

49
drivers/gpu/drm/imx/sec_mipi_pll_1432x.h 100644
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@ -0,0 +1,49 @@
/*
* Samsung MIPI DSIM PLL_1432X
*
* Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SEC_DSIM_PLL_1432X_H__
#define __SEC_DSIM_PLL_1432X_H__
#include <drm/bridge/sec_mipi_dsim.h>
/*
* DSIM PLL_1432X setting guide from spec:
*
* Fout(bitclk) = ((m + k / 65536) * Fin) / (p * 2^s), and
* p = P[5:0], m = M[9:0], s = S[2:0], k = K[15:0];
*
* Fpref = Fin / p
* Fin: [6MHz ~ 300MHz], Fpref: [2MHz ~ 30MHz]
*
* Fvco = ((m + k / 65536) * Fin) / p
* Fvco: [1050MHz ~ 2100MHz]
*
* 1 <= P[5:0] <= 63, 64 <= M[9:0] <= 1023,
* 0 <= S[2:0] <= 5, -32768 <= K[15:0] <= 32767
*
*/
const struct sec_mipi_dsim_pll pll_1432x = {
.p = { .min = 1, .max = 63, },
.m = { .min = 64, .max = 1023, },
.s = { .min = 0, .max = 5, },
.k = { .min = 0, .max = 32768, }, /* abs(k) */
.fin = { .min = 6000, .max = 300000, }, /* in KHz */
.fpref = { .min = 2000, .max = 30000, }, /* in KHz */
.fvco = { .min = 1050000, .max = 2100000, }, /* in KHz */
};
#endif