arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623
Modify audio related nodes to reflect the actual usage in binding documents. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>hifive-unleashed-5.1
Ryder Lee
Matthias Brugger
parent
60cc43fc88
commit
8eef6dea7c
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@ -426,104 +426,96 @@
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status = "disabled";
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};
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afe: audio-controller@11220000 {
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compatible = "mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112a0000 0 0x20000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt2701-audsys", "syscon";
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reg = <0 0x11220000 0 0x2000>;
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#clock-cells = <1>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
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<&topckgen CLK_TOP_APLL_SEL>,
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<&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>,
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<&topckgen CLK_TOP_HADDS2PLL_98M>,
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<&topckgen CLK_TOP_HADDS2PLL_294M>,
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<&topckgen CLK_TOP_AUDPLL>,
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<&topckgen CLK_TOP_AUDPLL_D4>,
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<&topckgen CLK_TOP_AUDPLL_D8>,
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<&topckgen CLK_TOP_AUDPLL_D16>,
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<&topckgen CLK_TOP_AUDPLL_D24>,
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<&topckgen CLK_TOP_AUDINTBUS_SEL>,
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<&clk26m>,
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<&topckgen CLK_TOP_SYSPLL1_D4>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
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<&topckgen CLK_TOP_ASM_M_SEL>,
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<&topckgen CLK_TOP_ASM_H_SEL>,
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<&topckgen CLK_TOP_UNIVPLL2_D4>,
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<&topckgen CLK_TOP_UNIVPLL2_D2>,
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<&topckgen CLK_TOP_SYSPLL_D5>;
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afe: audio-controller {
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compatible = "mediatek,mt2701-audio";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_mux1_div",
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"top_audio_mux2_div",
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"top_audio_48k_timing",
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"top_audio_44k_timing",
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"top_audpll_mux_sel",
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"top_apll_sel",
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"top_aud1_pll_98M",
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"top_aud2_pll_90M",
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"top_hadds2_pll_98M",
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"top_hadds2_pll_294M",
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"top_audpll",
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"top_audpll_d4",
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"top_audpll_d8",
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"top_audpll_d16",
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"top_audpll_d24",
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"top_audintbus_sel",
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"clk_26m",
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"top_syspll1_d4",
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"top_aud_k1_src_sel",
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"top_aud_k2_src_sel",
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"top_aud_k3_src_sel",
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"top_aud_k4_src_sel",
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"top_aud_k5_src_sel",
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"top_aud_k6_src_sel",
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"top_aud_k1_src_div",
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"top_aud_k2_src_div",
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"top_aud_k3_src_div",
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"top_aud_k4_src_div",
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"top_aud_k5_src_div",
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"top_aud_k6_src_div",
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"top_aud_i2s1_mclk",
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"top_aud_i2s2_mclk",
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"top_aud_i2s3_mclk",
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"top_aud_i2s4_mclk",
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"top_aud_i2s5_mclk",
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"top_aud_i2s6_mclk",
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"top_asm_m_sel",
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"top_asm_h_sel",
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"top_univpll2_d4",
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"top_univpll2_d2",
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"top_syspll_d5";
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&audsys CLK_AUD_I2SO1>,
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<&audsys CLK_AUD_I2SO2>,
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<&audsys CLK_AUD_I2SO3>,
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<&audsys CLK_AUD_I2SO4>,
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<&audsys CLK_AUD_I2SIN1>,
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<&audsys CLK_AUD_I2SIN2>,
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<&audsys CLK_AUD_I2SIN3>,
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<&audsys CLK_AUD_I2SIN4>,
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<&audsys CLK_AUD_ASRCO1>,
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<&audsys CLK_AUD_ASRCO2>,
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<&audsys CLK_AUD_ASRCO3>,
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<&audsys CLK_AUD_ASRCO4>,
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<&audsys CLK_AUD_AFE>,
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<&audsys CLK_AUD_AFE_CONN>,
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<&audsys CLK_AUD_A1SYS>,
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<&audsys CLK_AUD_A2SYS>,
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<&audsys CLK_AUD_AFE_MRGIF>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
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"i2s0_mclk_en",
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"i2s1_mclk_en",
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"i2s2_mclk_en",
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"i2s3_mclk_en",
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"i2so0_hop_ck",
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"i2so1_hop_ck",
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"i2so2_hop_ck",
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"i2so3_hop_ck",
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"i2si0_hop_ck",
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"i2si1_hop_ck",
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"i2si2_hop_ck",
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"i2si3_hop_ck",
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"asrc0_out_ck",
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"asrc1_out_ck",
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"asrc2_out_ck",
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"asrc3_out_ck",
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"audio_afe_pd",
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"audio_afe_conn_pd",
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"audio_a1sys_pd",
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"audio_a2sys_pd",
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"audio_mrgif_pd";
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assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>;
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assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>;
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assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
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};
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};
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mmsys: syscon@14000000 {
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@ -545,105 +545,99 @@
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status = "disabled";
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};
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afe: audio-controller@11220000 {
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compatible = "mediatek,mt7623-audio",
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"mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112a0000 0 0x20000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt7623-audsys",
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"mediatek,mt2701-audsys",
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"syscon";
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reg = <0 0x11220000 0 0x2000>;
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#clock-cells = <1>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
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<&topckgen CLK_TOP_APLL_SEL>,
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<&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>,
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<&topckgen CLK_TOP_HADDS2PLL_98M>,
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<&topckgen CLK_TOP_HADDS2PLL_294M>,
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<&topckgen CLK_TOP_AUDPLL>,
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<&topckgen CLK_TOP_AUDPLL_D4>,
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<&topckgen CLK_TOP_AUDPLL_D8>,
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<&topckgen CLK_TOP_AUDPLL_D16>,
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<&topckgen CLK_TOP_AUDPLL_D24>,
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<&topckgen CLK_TOP_AUDINTBUS_SEL>,
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<&clk26m>,
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<&topckgen CLK_TOP_SYSPLL1_D4>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
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<&topckgen CLK_TOP_ASM_M_SEL>,
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<&topckgen CLK_TOP_ASM_H_SEL>,
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<&topckgen CLK_TOP_UNIVPLL2_D4>,
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<&topckgen CLK_TOP_UNIVPLL2_D2>,
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<&topckgen CLK_TOP_SYSPLL_D5>;
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afe: audio-controller {
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compatible = "mediatek,mt7623-audio",
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"mediatek,mt2701-audio";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_mux1_div",
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"top_audio_mux2_div",
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"top_audio_48k_timing",
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"top_audio_44k_timing",
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"top_audpll_mux_sel",
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"top_apll_sel",
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"top_aud1_pll_98M",
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"top_aud2_pll_90M",
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"top_hadds2_pll_98M",
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"top_hadds2_pll_294M",
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"top_audpll",
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"top_audpll_d4",
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"top_audpll_d8",
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"top_audpll_d16",
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"top_audpll_d24",
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"top_audintbus_sel",
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"clk_26m",
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"top_syspll1_d4",
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"top_aud_k1_src_sel",
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"top_aud_k2_src_sel",
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"top_aud_k3_src_sel",
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"top_aud_k4_src_sel",
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"top_aud_k5_src_sel",
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"top_aud_k6_src_sel",
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"top_aud_k1_src_div",
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"top_aud_k2_src_div",
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"top_aud_k3_src_div",
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"top_aud_k4_src_div",
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"top_aud_k5_src_div",
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"top_aud_k6_src_div",
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"top_aud_i2s1_mclk",
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"top_aud_i2s2_mclk",
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"top_aud_i2s3_mclk",
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"top_aud_i2s4_mclk",
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"top_aud_i2s5_mclk",
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"top_aud_i2s6_mclk",
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"top_asm_m_sel",
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"top_asm_h_sel",
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"top_univpll2_d4",
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"top_univpll2_d2",
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"top_syspll_d5";
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&audsys CLK_AUD_I2SO1>,
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<&audsys CLK_AUD_I2SO2>,
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<&audsys CLK_AUD_I2SO3>,
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<&audsys CLK_AUD_I2SO4>,
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<&audsys CLK_AUD_I2SIN1>,
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<&audsys CLK_AUD_I2SIN2>,
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<&audsys CLK_AUD_I2SIN3>,
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<&audsys CLK_AUD_I2SIN4>,
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<&audsys CLK_AUD_ASRCO1>,
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<&audsys CLK_AUD_ASRCO2>,
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<&audsys CLK_AUD_ASRCO3>,
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<&audsys CLK_AUD_ASRCO4>,
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<&audsys CLK_AUD_AFE>,
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<&audsys CLK_AUD_AFE_CONN>,
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<&audsys CLK_AUD_A1SYS>,
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<&audsys CLK_AUD_A2SYS>,
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<&audsys CLK_AUD_AFE_MRGIF>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
|
||||
"i2s0_mclk_en",
|
||||
"i2s1_mclk_en",
|
||||
"i2s2_mclk_en",
|
||||
"i2s3_mclk_en",
|
||||
"i2so0_hop_ck",
|
||||
"i2so1_hop_ck",
|
||||
"i2so2_hop_ck",
|
||||
"i2so3_hop_ck",
|
||||
"i2si0_hop_ck",
|
||||
"i2si1_hop_ck",
|
||||
"i2si2_hop_ck",
|
||||
"i2si3_hop_ck",
|
||||
"asrc0_out_ck",
|
||||
"asrc1_out_ck",
|
||||
"asrc2_out_ck",
|
||||
"asrc3_out_ck",
|
||||
"audio_afe_pd",
|
||||
"audio_afe_conn_pd",
|
||||
"audio_a1sys_pd",
|
||||
"audio_a2sys_pd",
|
||||
"audio_mrgif_pd";
|
||||
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
|
||||
<&topckgen CLK_TOP_AUD2PLL_90M>;
|
||||
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
|
|
|
|||
Loading…
Reference in New Issue