drm/i915: Fold intel_ironlake_limit() into clock computation function
The function intel_ironlake_limit() is only called by the crtc compute clock path. By merging it into ironlake_compute_clocks(), the code gets clearer, since there's no more if-ladders to follow. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-4-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -565,30 +565,6 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
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return false;
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}
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static const intel_limit_t *
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intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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const intel_limit_t *limit;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_is_dual_link_lvds(dev)) {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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else
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limit = &intel_limits_ironlake_dual_lvds;
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} else {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_single_lvds_100m;
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else
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limit = &intel_limits_ironlake_single_lvds;
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}
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} else
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limit = &intel_limits_ironlake_dac;
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return limit;
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}
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static const intel_limit_t *
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intel_g4x_limit(struct intel_crtc_state *crtc_state)
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{
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@ -619,8 +595,8 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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if (IS_BROXTON(dev))
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limit = &intel_limits_bxt;
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else if (HAS_PCH_SPLIT(dev))
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limit = intel_ironlake_limit(crtc_state, refclk);
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else if (WARN_ON(HAS_PCH_SPLIT(dev)))
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limit = NULL;
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else if (IS_G4X(dev)) {
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limit = intel_g4x_limit(crtc_state);
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} else if (IS_PINEVIEW(dev)) {
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@ -8671,13 +8647,28 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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const intel_limit_t *limit;
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bool ret;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
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dev_priv->vbt.lvds_ssc_freq);
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refclk = dev_priv->vbt.lvds_ssc_freq;
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refclk = 120000;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
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dev_priv->vbt.lvds_ssc_freq);
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refclk = dev_priv->vbt.lvds_ssc_freq;
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}
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if (intel_is_dual_link_lvds(dev)) {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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else
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limit = &intel_limits_ironlake_dual_lvds;
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} else {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_single_lvds_100m;
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else
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limit = &intel_limits_ironlake_single_lvds;
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}
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} else {
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refclk = 120000;
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limit = &intel_limits_ironlake_dac;
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}
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/*
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@ -8685,7 +8676,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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limit = intel_limit(crtc_state, refclk);
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ret = dev_priv->display.find_dpll(limit, crtc_state,
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crtc_state->port_clock,
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refclk, NULL, clock);
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