staging: olpc_dcon: drop XO-1.5 prototype support
Remove code related to XO-1.5 prototype boards. Signed-off-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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31a3da4146
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@ -10,19 +10,15 @@
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/* Hardware setup on the XO 1.5:
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/* Hardware setup on the XO 1.5:
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* DCONLOAD connects to
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* DCONLOAD connects to
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* VX855_GPO12 (not nCR_PWOFF) (rev A)
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* VX855_GPIO1 (not SMBCK2)
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* VX855_GPIO1 (not SMBCK2) (rev B)
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* DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
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* DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
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* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
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* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
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* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
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* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
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* DCONIRQ connects to VX855_GPIO12 (on B3. on B2, it goes to
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* DCONIRQ connects to VX855_GPIO12
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* SMBALRT, which doesn't work.)
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* DCONSMBDATA connects to VX855 graphics CRTSPD
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* DCONSMBDATA connects to VX855 graphics CRTSPD
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* DCONSMBCLK connects to VX855 graphics CRTSPCLK
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* DCONSMBCLK connects to VX855 graphics CRTSPCLK
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*/
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*/
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#define TEST_B2 0 // define to test B3 paths on a modded B2 board
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#define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
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#define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
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#define VX855_GPI_STATUS_CHG 0x450 // PMIO_Rx50
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#define VX855_GPI_STATUS_CHG 0x450 // PMIO_Rx50
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#define VX855_GPI_SCI_SMI 0x452 // PMIO_Rx52
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#define VX855_GPI_SCI_SMI 0x452 // PMIO_Rx52
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@ -30,34 +26,21 @@
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#define PREFIX "OLPC DCON:"
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#define PREFIX "OLPC DCON:"
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/*
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there is no support here for DCONIRQ on 1.5 boards earlier than
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B3. the issue is that the DCONIRQ signal on earlier boards is
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routed to SMBALRT, which turns out to to be a level sensitive
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interrupt. the DCONIRQ signal is far too short (11usec) to
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be detected reliably in that case. including support for
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DCONIRQ functions no better than none at all.
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*/
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static struct dcon_platform_data dcon_pdata_xo_1_5;
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static struct dcon_platform_data dcon_pdata_xo_1_5;
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static void dcon_clear_irq(void)
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static void dcon_clear_irq(void)
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{
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{
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if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
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/* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
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// irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12
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outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
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outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
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}
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}
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}
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static int dcon_was_irq(void)
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static int dcon_was_irq(void)
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{
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{
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u_int8_t tmp;
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u_int8_t tmp;
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if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
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/* irq status will appear in PMIO_Rx50[6] on gpio12 */
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// irq status will appear in PMIO_Rx50[6] on gpio12
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tmp = inb(VX855_GPI_STATUS_CHG);
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tmp = inb(VX855_GPI_STATUS_CHG);
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return !!(tmp & BIT_GPIO12);
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return !!(tmp & BIT_GPIO12);
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}
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return 0;
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return 0;
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}
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}
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@ -76,14 +59,8 @@ static int dcon_init_xo_1_5(void)
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return 1;
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return 1;
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}
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}
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if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
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pci_read_config_byte(pdev, 0x95, &tmp);
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pci_read_config_byte(pdev, 0x95, &tmp);
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pci_write_config_byte(pdev, 0x95, tmp|0x0c);
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pci_write_config_byte(pdev, 0x95, tmp|0x0c);
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} else {
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/* Set GPO12 to GPO mode, not nCR_PWOFF */
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pci_read_config_byte(pdev, 0x9b, &tmp);
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pci_write_config_byte(pdev, 0x9b, tmp|0x01);
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}
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/* Set GPIO8 to GPIO mode, not SSPICLK */
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/* Set GPIO8 to GPIO mode, not SSPICLK */
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pci_read_config_byte(pdev, 0xe3, &tmp);
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pci_read_config_byte(pdev, 0xe3, &tmp);
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@ -93,31 +70,22 @@ static int dcon_init_xo_1_5(void)
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pci_read_config_byte(pdev, 0xe4, &tmp);
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pci_read_config_byte(pdev, 0xe4, &tmp);
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pci_write_config_byte(pdev, 0xe4, tmp|0x08);
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pci_write_config_byte(pdev, 0xe4, tmp|0x08);
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if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
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/* clear PMU_RxE1[6] to select SCI on GPIO12 */
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// clear PMU_RxE1[6] to select SCI on GPIO12
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/* clear PMU_RxE0[6] to choose falling edge */
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// clear PMU_RxE0[6] to choose falling edge
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pci_read_config_byte(pdev, 0xe1, &tmp);
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pci_read_config_byte(pdev, 0xe1, &tmp);
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pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
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pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
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pci_read_config_byte(pdev, 0xe0, &tmp);
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pci_read_config_byte(pdev, 0xe0, &tmp);
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pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
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pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
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dcon_clear_irq();
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dcon_clear_irq();
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// set PMIO_Rx52[6] to enable SCI/SMI on gpio12
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/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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}
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/* Determine the current state of DCONLOAD, likely set by firmware */
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/* Determine the current state of DCONLOAD, likely set by firmware */
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if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
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/* GPIO1 */
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// GPIO1
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dcon_source = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
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dcon_source = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
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DCON_SOURCE_CPU : DCON_SOURCE_DCON;
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DCON_SOURCE_CPU : DCON_SOURCE_DCON;
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} else {
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// GPO12
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dcon_source = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x04000000) ?
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DCON_SOURCE_CPU : DCON_SOURCE_DCON;
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}
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dcon_pending = dcon_source;
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dcon_pending = dcon_source;
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pci_dev_put(pdev);
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pci_dev_put(pdev);
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@ -180,19 +148,13 @@ static void dcon_wiggle_xo_1_5(void)
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}
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}
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udelay(5);
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udelay(5);
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if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
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/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
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// set PMIO_Rx52[6] to enable SCI/SMI on gpio12
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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}
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}
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}
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static void dcon_set_dconload_xo_1_5(int val)
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static void dcon_set_dconload_xo_1_5(int val)
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{
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{
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if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
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gpio_set_value(VX855_GPIO(1), val);
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gpio_set_value(VX855_GPIO(1), val);
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} else {
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gpio_set_value(VX855_GPO(12), val);
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}
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}
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}
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static u8 dcon_read_status_xo_1_5(void)
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static u8 dcon_read_status_xo_1_5(void)
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