Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar. * 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: arm_mhu: add driver for ARM MHU controller Mailbox: Restructure and simplify PCC mailbox code
This commit is contained in:
Linus Torvalds
commit
8fa6f4974d
43
Documentation/devicetree/bindings/mailbox/arm-mhu.txt
Normal file
43
Documentation/devicetree/bindings/mailbox/arm-mhu.txt
Normal file
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|
@ -0,0 +1,43 @@
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ARM MHU Mailbox Driver
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======================
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The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
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3 independent channels/links to communicate with remote processor(s).
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MHU links are hardwired on a platform. A link raises interrupt for any
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received data. However, there is no specified way of knowing if the sent
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data has been read by the remote. This driver assumes the sender polls
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STAT register and the remote clears it after having read the data.
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The last channel is specified to be a 'Secure' resource, hence can't be
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used by Linux running NS.
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Mailbox Device Node:
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====================
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Required properties:
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--------------------
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- compatible: Shall be "arm,mhu" & "arm,primecell"
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- reg: Contains the mailbox register address range (base
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address and length)
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- #mbox-cells Shall be 1 - the index of the channel needed.
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- interrupts: Contains the interrupt information corresponding to
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each of the 3 links of MHU.
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Example:
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--------
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mhu: mailbox@2b1f0000 {
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#mbox-cells = <1>;
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compatible = "arm,mhu", "arm,primecell";
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reg = <0 0x2b1f0000 0x1000>;
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interrupts = <0 36 4>, /* LP-NonSecure */
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<0 35 4>, /* HP-NonSecure */
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<0 37 4>; /* Secure */
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clocks = <&clock 0 2 1>;
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clock-names = "apb_pclk";
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};
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mhu_client: scb@2e000000 {
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compatible = "fujitsu,mb86s70-scb-1.0";
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reg = <0 0x2e000000 0x4000>;
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mboxes = <&mhu 1>; /* HP-NonSecure */
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};
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@ -6,6 +6,15 @@ menuconfig MAILBOX
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signals. Say Y if your platform supports hardware mailboxes.
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if MAILBOX
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config ARM_MHU
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tristate "ARM MHU Mailbox"
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depends on ARM_AMBA
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help
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Say Y here if you want to build the ARM MHU controller driver.
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The controller has 3 mailbox channels, the last of which can be
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used in Secure mode only.
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config PL320_MBOX
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bool "ARM PL320 Mailbox"
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depends on ARM_AMBA
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|
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@ -2,6 +2,8 @@
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obj-$(CONFIG_MAILBOX) += mailbox.o
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obj-$(CONFIG_ARM_MHU) += arm_mhu.o
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obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
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obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
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195
drivers/mailbox/arm_mhu.c
Normal file
195
drivers/mailbox/arm_mhu.c
Normal file
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@ -0,0 +1,195 @@
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/*
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* Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Jassi Brar <jaswinder.singh@linaro.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/amba/bus.h>
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#include <linux/mailbox_controller.h>
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#define INTR_STAT_OFS 0x0
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#define INTR_SET_OFS 0x8
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#define INTR_CLR_OFS 0x10
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#define MHU_LP_OFFSET 0x0
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#define MHU_HP_OFFSET 0x20
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#define MHU_SEC_OFFSET 0x200
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#define TX_REG_OFFSET 0x100
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#define MHU_CHANS 3
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struct mhu_link {
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unsigned irq;
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void __iomem *tx_reg;
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void __iomem *rx_reg;
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};
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struct arm_mhu {
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void __iomem *base;
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struct mhu_link mlink[MHU_CHANS];
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struct mbox_chan chan[MHU_CHANS];
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struct mbox_controller mbox;
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};
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static irqreturn_t mhu_rx_interrupt(int irq, void *p)
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{
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struct mbox_chan *chan = p;
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struct mhu_link *mlink = chan->con_priv;
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u32 val;
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val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
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if (!val)
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return IRQ_NONE;
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mbox_chan_received_data(chan, (void *)&val);
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writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
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return IRQ_HANDLED;
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}
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static bool mhu_last_tx_done(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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return (val == 0);
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}
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static int mhu_send_data(struct mbox_chan *chan, void *data)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 *arg = data;
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writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
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return 0;
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}
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static int mhu_startup(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 val;
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int ret;
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val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
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ret = request_irq(mlink->irq, mhu_rx_interrupt,
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IRQF_SHARED, "mhu_link", chan);
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if (ret) {
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dev_err(chan->mbox->dev,
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"Unable to aquire IRQ %d\n", mlink->irq);
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return ret;
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}
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return 0;
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}
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static void mhu_shutdown(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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free_irq(mlink->irq, chan);
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}
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static struct mbox_chan_ops mhu_ops = {
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.send_data = mhu_send_data,
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.startup = mhu_startup,
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.shutdown = mhu_shutdown,
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.last_tx_done = mhu_last_tx_done,
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};
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static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
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{
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int i, err;
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struct arm_mhu *mhu;
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struct device *dev = &adev->dev;
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int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
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|
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/* Allocate memory for device */
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mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
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if (!mhu)
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return -ENOMEM;
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|
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mhu->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(mhu->base)) {
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dev_err(dev, "ioremap failed\n");
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return PTR_ERR(mhu->base);
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}
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for (i = 0; i < MHU_CHANS; i++) {
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mhu->chan[i].con_priv = &mhu->mlink[i];
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mhu->mlink[i].irq = adev->irq[i];
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mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
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mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
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}
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mhu->mbox.dev = dev;
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mhu->mbox.chans = &mhu->chan[0];
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mhu->mbox.num_chans = MHU_CHANS;
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mhu->mbox.ops = &mhu_ops;
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mhu->mbox.txdone_irq = false;
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mhu->mbox.txdone_poll = true;
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mhu->mbox.txpoll_period = 10;
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|
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amba_set_drvdata(adev, mhu);
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err = mbox_controller_register(&mhu->mbox);
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if (err) {
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dev_err(dev, "Failed to register mailboxes %d\n", err);
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return err;
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}
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dev_info(dev, "ARM MHU Mailbox registered\n");
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return 0;
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}
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static int mhu_remove(struct amba_device *adev)
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{
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struct arm_mhu *mhu = amba_get_drvdata(adev);
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mbox_controller_unregister(&mhu->mbox);
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return 0;
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}
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static struct amba_id mhu_ids[] = {
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{
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.id = 0x1bb098,
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.mask = 0xffffff,
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},
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{ 0, 0 },
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};
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MODULE_DEVICE_TABLE(amba, mhu_ids);
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static struct amba_driver arm_mhu_driver = {
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.drv = {
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.name = "mhu",
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},
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.id_table = mhu_ids,
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.probe = mhu_probe,
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.remove = mhu_remove,
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};
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module_amba_driver(arm_mhu_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("ARM MHU Driver");
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MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");
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|
@ -20,10 +20,35 @@
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* shared memory regions as defined in the PCC table entries. The PCC
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* specification supports a Doorbell mechanism for the PCC clients
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* to notify the platform about new data. This Doorbell information
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* is also specified in each PCC table entry. See pcc_send_data()
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* and pcc_tx_done() for basic mode of operation.
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* is also specified in each PCC table entry.
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*
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* For more details about PCC, please see the ACPI specification from
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* Typical high level flow of operation is:
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*
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* PCC Reads:
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* * Client tries to acquire a channel lock.
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* * After it is acquired it writes READ cmd in communication region cmd
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* address.
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* * Client issues mbox_send_message() which rings the PCC doorbell
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* for its PCC channel.
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* * If command completes, then client has control over channel and
|
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* it can proceed with its reads.
|
||||
* * Client releases lock.
|
||||
*
|
||||
* PCC Writes:
|
||||
* * Client tries to acquire channel lock.
|
||||
* * Client writes to its communication region after it acquires a
|
||||
* channel lock.
|
||||
* * Client writes WRITE cmd in communication region cmd address.
|
||||
* * Client issues mbox_send_message() which rings the PCC doorbell
|
||||
* for its PCC channel.
|
||||
* * If command completes, then writes have succeded and it can release
|
||||
* the channel lock.
|
||||
*
|
||||
* There is a Nominal latency defined for each channel which indicates
|
||||
* how long to wait until a command completes. If command is not complete
|
||||
* the client needs to retry or assume failure.
|
||||
*
|
||||
* For more details about PCC, please see the ACPI specification from
|
||||
* http://www.uefi.org/ACPIv5.1 Section 14.
|
||||
*
|
||||
* This file implements PCC as a Mailbox controller and allows for PCC
|
||||
|
|
@ -42,8 +67,6 @@
|
|||
#include "mailbox.h"
|
||||
|
||||
#define MAX_PCC_SUBSPACES 256
|
||||
#define PCCS_SS_SIG_MAGIC 0x50434300
|
||||
#define PCC_CMD_COMPLETE 0x1
|
||||
|
||||
static struct mbox_chan *pcc_mbox_channels;
|
||||
|
||||
|
|
@ -70,23 +93,6 @@ static struct mbox_chan *get_pcc_channel(int id)
|
|||
return pcc_chan;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_subspace_id - Given a Mailbox channel, find out the
|
||||
* PCC subspace id.
|
||||
* @chan: Pointer to Mailbox Channel from which we want
|
||||
* the index.
|
||||
* Return: Errno if not found, else positive index number.
|
||||
*/
|
||||
static int get_subspace_id(struct mbox_chan *chan)
|
||||
{
|
||||
unsigned int id = chan - pcc_mbox_channels;
|
||||
|
||||
if (id < 0 || id > pcc_mbox_ctrl.num_chans)
|
||||
return -ENOENT;
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcc_mbox_request_channel - PCC clients call this function to
|
||||
* request a pointer to their PCC subspace, from which they
|
||||
|
|
@ -117,7 +123,7 @@ struct mbox_chan *pcc_mbox_request_channel(struct mbox_client *cl,
|
|||
chan = get_pcc_channel(subspace_id);
|
||||
|
||||
if (!chan || chan->cl) {
|
||||
dev_err(dev, "%s: PCC mailbox not free\n", __func__);
|
||||
dev_err(dev, "Channel not found for idx: %d\n", subspace_id);
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
|
|
@ -161,81 +167,30 @@ void pcc_mbox_free_channel(struct mbox_chan *chan)
|
|||
EXPORT_SYMBOL_GPL(pcc_mbox_free_channel);
|
||||
|
||||
/**
|
||||
* pcc_tx_done - Callback from Mailbox controller code to
|
||||
* check if PCC message transmission completed.
|
||||
* @chan: Pointer to Mailbox channel on which previous
|
||||
* transmission occurred.
|
||||
*
|
||||
* Return: TRUE if succeeded.
|
||||
*/
|
||||
static bool pcc_tx_done(struct mbox_chan *chan)
|
||||
{
|
||||
struct acpi_pcct_hw_reduced *pcct_ss = chan->con_priv;
|
||||
struct acpi_pcct_shared_memory *generic_comm_base =
|
||||
(struct acpi_pcct_shared_memory *) pcct_ss->base_address;
|
||||
u16 cmd_delay = pcct_ss->latency;
|
||||
unsigned int retries = 0;
|
||||
|
||||
/* Try a few times while waiting for platform to consume */
|
||||
while (!(readw_relaxed(&generic_comm_base->status)
|
||||
& PCC_CMD_COMPLETE)) {
|
||||
|
||||
if (retries++ < 5)
|
||||
udelay(cmd_delay);
|
||||
else {
|
||||
/*
|
||||
* If the remote is dead, this will cause the Mbox
|
||||
* controller to timeout after mbox client.tx_tout
|
||||
* msecs.
|
||||
*/
|
||||
pr_err("PCC platform did not respond.\n");
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcc_send_data - Called from Mailbox Controller code to finally
|
||||
* transmit data over channel.
|
||||
* pcc_send_data - Called from Mailbox Controller code. Used
|
||||
* here only to ring the channel doorbell. The PCC client
|
||||
* specific read/write is done in the client driver in
|
||||
* order to maintain atomicity over PCC channel once
|
||||
* OS has control over it. See above for flow of operations.
|
||||
* @chan: Pointer to Mailbox channel over which to send data.
|
||||
* @data: Actual data to be written over channel.
|
||||
* @data: Client specific data written over channel. Used here
|
||||
* only for debug after PCC transaction completes.
|
||||
*
|
||||
* Return: Err if something failed else 0 for success.
|
||||
*/
|
||||
static int pcc_send_data(struct mbox_chan *chan, void *data)
|
||||
{
|
||||
struct acpi_pcct_hw_reduced *pcct_ss = chan->con_priv;
|
||||
struct acpi_pcct_shared_memory *generic_comm_base =
|
||||
(struct acpi_pcct_shared_memory *) pcct_ss->base_address;
|
||||
struct acpi_generic_address doorbell;
|
||||
u64 doorbell_preserve;
|
||||
u64 doorbell_val;
|
||||
u64 doorbell_write;
|
||||
u16 cmd = *(u16 *) data;
|
||||
u16 ss_idx = -1;
|
||||
|
||||
ss_idx = get_subspace_id(chan);
|
||||
|
||||
if (ss_idx < 0) {
|
||||
pr_err("Invalid Subspace ID from PCC client\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
doorbell = pcct_ss->doorbell_register;
|
||||
doorbell_preserve = pcct_ss->preserve_mask;
|
||||
doorbell_write = pcct_ss->write_mask;
|
||||
|
||||
/* Write to the shared comm region. */
|
||||
writew(cmd, &generic_comm_base->command);
|
||||
|
||||
/* Write Subspace MAGIC value so platform can identify destination. */
|
||||
writel((PCCS_SS_SIG_MAGIC | ss_idx), &generic_comm_base->signature);
|
||||
|
||||
/* Flip CMD COMPLETE bit */
|
||||
writew(0, &generic_comm_base->status);
|
||||
|
||||
/* Sync notification from OSPM to Platform. */
|
||||
/* Sync notification from OS to Platform. */
|
||||
acpi_read(&doorbell_val, &doorbell);
|
||||
acpi_write((doorbell_val & doorbell_preserve) | doorbell_write,
|
||||
&doorbell);
|
||||
|
|
@ -245,7 +200,6 @@ static int pcc_send_data(struct mbox_chan *chan, void *data)
|
|||
|
||||
static struct mbox_chan_ops pcc_chan_ops = {
|
||||
.send_data = pcc_send_data,
|
||||
.last_tx_done = pcc_tx_done,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -351,8 +305,6 @@ static int pcc_mbox_probe(struct platform_device *pdev)
|
|||
|
||||
pcc_mbox_ctrl.chans = pcc_mbox_channels;
|
||||
pcc_mbox_ctrl.ops = &pcc_chan_ops;
|
||||
pcc_mbox_ctrl.txdone_poll = true;
|
||||
pcc_mbox_ctrl.txpoll_period = 10;
|
||||
pcc_mbox_ctrl.dev = &pdev->dev;
|
||||
|
||||
pr_info("Registering PCC driver as Mailbox controller\n");
|
||||
|
|
|
|||
Loading…
Reference in a new issue