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ARM: dts: r8a7791: Add L2 cache-controller node 

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
hifive-unleashed-5.1
Geert Uytterhoeven 2015-06-02 14:33:46 +02:00 committed by Simon Horman
parent fb1cecd406
commit 8ffe93a5b2
1 changed files with 8 additions and 0 deletions
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8
arch/arm/boot/dts/r8a7791.dtsi
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@ -51,6 +51,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7791_CLK_Z>;
clock-latency = <300000>; /* 300 us */
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@ -66,6 +67,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
next-level-cache = <&L2_CA15>;
};
};
@ -88,6 +90,12 @@
};
};
L2_CA15: cache-controller@0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;